SolarLader/SolarLader_Hardware
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SolarLader_Hardware/SolarLader.kicad_pcb

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Completed routing iteration
2016-06-27 21:55:33 +02:00
(kicad_pcb (version 4) (host pcbnew 4.0.2-stable)
Initial commit - Full schematic - Partially placed board
2016-06-26 00:26:23 +02:00
(general
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(links 132)
(no_connects 0)
(area 17.450999 15.926999 70.814001 72.465001)
(thickness 0.8)
Added C for current meas. opamp
2016-06-29 23:00:58 +02:00
(drawings 9)
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(tracks 538)
Initial commit - Full schematic - Partially placed board
2016-06-26 00:26:23 +02:00
(zones 0)
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(modules 63)
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(nets 55)
Initial commit - Full schematic - Partially placed board
2016-06-26 00:26:23 +02:00
)
(page A4)
(layers
(0 F.Cu signal)
(31 B.Cu signal)
(32 B.Adhes user)
(33 F.Adhes user)
(34 B.Paste user)
(35 F.Paste user)
(36 B.SilkS user)
(37 F.SilkS user)
(38 B.Mask user)
(39 F.Mask user)
(40 Dwgs.User user)
(41 Cmts.User user)
(42 Eco1.User user)
(43 Eco2.User user)
(44 Edge.Cuts user)
(45 Margin user)
(46 B.CrtYd user)
(47 F.CrtYd user)
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(48 B.Fab user)
(49 F.Fab user)
Initial commit - Full schematic - Partially placed board
2016-06-26 00:26:23 +02:00
)
(setup
Pimped silkscreen a little
2016-07-03 17:50:25 +02:00
(last_trace_width 0.3)
Completed routing iteration
2016-06-27 21:55:33 +02:00
(user_trace_width 0.5)
(user_trace_width 1)
Initial commit - Full schematic - Partially placed board
2016-06-26 00:26:23 +02:00
(trace_clearance 0.2)
Completed routing iteration
2016-06-27 21:55:33 +02:00
(zone_clearance 0.4)
Initial commit - Full schematic - Partially placed board
2016-06-26 00:26:23 +02:00
(zone_45_only no)
Added C for current meas. opamp
2016-06-29 23:00:58 +02:00
(trace_min 0.25)
Initial commit - Full schematic - Partially placed board
2016-06-26 00:26:23 +02:00
(segment_width 0.2)
(edge_width 0.15)
(via_size 0.6)
(via_drill 0.4)
(via_min_size 0.4)
(via_min_drill 0.3)
(uvia_size 0.3)
(uvia_drill 0.1)
(uvias_allowed no)
(uvia_min_size 0.2)
(uvia_min_drill 0.1)
(pcb_text_width 0.3)
(pcb_text_size 1.5 1.5)
(mod_edge_width 0.15)
(mod_text_size 1 1)
(mod_text_width 0.15)
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(pad_size 5 5)
(pad_drill 3.2)
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(pad_to_mask_clearance 0.1)
Initial commit - Full schematic - Partially placed board
2016-06-26 00:26:23 +02:00
(aux_axis_origin 0 0)
(visible_elements FFFFFF7F)
(pcbplotparams
Final fixes before fab
2016-07-03 23:52:32 +02:00
(layerselection 0x010f0_80000001)
Initial commit - Full schematic - Partially placed board
2016-06-26 00:26:23 +02:00
(usegerberextensions false)
(excludeedgelayer true)
(linewidth 0.100000)
(plotframeref false)
(viasonmask false)
(mode 1)
(useauxorigin false)
(hpglpennumber 1)
(hpglpenspeed 20)
(hpglpendiameter 15)
(hpglpenoverlay 2)
(psnegative false)
(psa4output false)
(plotreference true)
(plotvalue true)
(plotinvisibletext false)
(padsonsilk false)
(subtractmaskfromsilk false)
(outputformat 1)
(mirror false)
Final fixes before fab
2016-07-03 23:52:32 +02:00
(drillshape 0)
Initial commit - Full schematic - Partially placed board
2016-06-26 00:26:23 +02:00
(scaleselection 1)
Final fixes before fab
2016-07-03 23:52:32 +02:00
(outputdirectory fab/))
Initial commit - Full schematic - Partially placed board
2016-06-26 00:26:23 +02:00
)
(net 0 "")
(net 1 +BATT)
(net 2 GND)
(net 3 +12V)
(net 4 +5V)
(net 5 +3V3)
(net 6 "Net-(C201-Pad1)")
(net 7 "Net-(C202-Pad1)")
(net 8 "Net-(C302-Pad1)")
(net 9 "Net-(C302-Pad2)")
(net 10 "/Power Converter/VInDirect")
(net 11 "/Power Converter/Bat-")
(net 12 "Net-(D301-Pad1)")
(net 13 "/Power Converter/Vpanel")
(net 14 "/Power Converter/Load-")
(net 15 /Mikrocontroller/UART_TX)
(net 16 /Mikrocontroller/UART_RX)
(net 17 /Mikrocontroller/SWCLK)
(net 18 /Mikrocontroller/SWDIO)
(net 19 /Mikrocontroller/RST_N)
(net 20 "Net-(P202-Pad6)")
(net 21 /Mikrocontroller/DISP_CONTRAST)
(net 22 /Mikrocontroller/DISP_RS)
(net 23 /Mikrocontroller/DISP_RW)
(net 24 /Mikrocontroller/DISP_E)
(net 25 "Net-(P203-Pad7)")
(net 26 "Net-(P203-Pad8)")
(net 27 "Net-(P203-Pad9)")
(net 28 "Net-(P203-Pad10)")
(net 29 /Mikrocontroller/DISP_D0)
(net 30 /Mikrocontroller/DISP_D1)
(net 31 /Mikrocontroller/DISP_D2)
(net 32 /Mikrocontroller/DISP_D3)
(net 33 "Net-(P203-Pad15)")
(net 34 "Net-(P203-Pad16)")
(net 35 "Net-(Q301-Pad1)")
(net 36 "Net-(Q302-Pad1)")
(net 37 "/Power Converter/LoadDrive")
(net 38 "Net-(R202-Pad1)")
(net 39 /Mikrocontroller/BootstrapPulse)
(net 40 /Mikrocontroller/VInSense)
(net 41 /Mikrocontroller/VOutSense)
(net 42 /Mikrocontroller/CurrentSense)
(net 43 "Net-(R307-Pad2)")
(net 44 /Mikrocontroller/SW_on)
(net 45 "Net-(U201-Pad28)")
(net 46 "Net-(U201-Pad27)")
(net 47 "Net-(U201-Pad26)")
(net 48 /Mikrocontroller/LOAD_on)
(net 49 "Net-(U201-Pad9)")
(net 50 "Net-(U201-Pad14)")
(net 51 "Net-(U201-Pad15)")
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(net 52 "Net-(R309-Pad1)")
(net 53 "Net-(R310-Pad1)")
(net 54 "Net-(R311-Pad2)")
Initial commit - Full schematic - Partially placed board
2016-06-26 00:26:23 +02:00
(net_class Default "This is the default net class."
(clearance 0.2)
Completed routing iteration
2016-06-27 21:55:33 +02:00
(trace_width 0.3)
Initial commit - Full schematic - Partially placed board
2016-06-26 00:26:23 +02:00
(via_dia 0.6)
(via_drill 0.4)
(uvia_dia 0.3)
(uvia_drill 0.1)
(add_net +12V)
(add_net +3V3)
(add_net +5V)
(add_net /Mikrocontroller/BootstrapPulse)
(add_net /Mikrocontroller/CurrentSense)
(add_net /Mikrocontroller/DISP_CONTRAST)
(add_net /Mikrocontroller/DISP_D0)
(add_net /Mikrocontroller/DISP_D1)
(add_net /Mikrocontroller/DISP_D2)
(add_net /Mikrocontroller/DISP_D3)
(add_net /Mikrocontroller/DISP_E)
(add_net /Mikrocontroller/DISP_RS)
(add_net /Mikrocontroller/DISP_RW)
(add_net /Mikrocontroller/LOAD_on)
(add_net /Mikrocontroller/RST_N)
(add_net /Mikrocontroller/SWCLK)
(add_net /Mikrocontroller/SWDIO)
(add_net /Mikrocontroller/SW_on)
(add_net /Mikrocontroller/UART_RX)
(add_net /Mikrocontroller/UART_TX)
(add_net /Mikrocontroller/VInSense)
(add_net /Mikrocontroller/VOutSense)
(add_net "/Power Converter/LoadDrive")
(add_net GND)
(add_net "Net-(C201-Pad1)")
(add_net "Net-(C202-Pad1)")
(add_net "Net-(C302-Pad1)")
(add_net "Net-(P202-Pad6)")
(add_net "Net-(P203-Pad10)")
(add_net "Net-(P203-Pad15)")
(add_net "Net-(P203-Pad16)")
(add_net "Net-(P203-Pad7)")
(add_net "Net-(P203-Pad8)")
(add_net "Net-(P203-Pad9)")
(add_net "Net-(Q301-Pad1)")
(add_net "Net-(Q302-Pad1)")
(add_net "Net-(R202-Pad1)")
(add_net "Net-(R307-Pad2)")
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(add_net "Net-(R309-Pad1)")
(add_net "Net-(R310-Pad1)")
(add_net "Net-(R311-Pad2)")
Initial commit - Full schematic - Partially placed board
2016-06-26 00:26:23 +02:00
(add_net "Net-(U201-Pad14)")
(add_net "Net-(U201-Pad15)")
(add_net "Net-(U201-Pad26)")
(add_net "Net-(U201-Pad27)")
(add_net "Net-(U201-Pad28)")
(add_net "Net-(U201-Pad9)")
)
Completed routing iteration
2016-06-27 21:55:33 +02:00
(net_class Power ""
(clearance 0.3)
(trace_width 2)
(via_dia 1)
(via_drill 0.6)
(uvia_dia 0.3)
(uvia_drill 0.1)
(add_net +BATT)
(add_net "/Power Converter/Bat-")
(add_net "/Power Converter/Load-")
(add_net "/Power Converter/VInDirect")
(add_net "/Power Converter/Vpanel")
(add_net "Net-(C302-Pad2)")
(add_net "Net-(D301-Pad1)")
)
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(module Logos:bytewerk_5mm_with_text (layer B.Cu) (tedit 0) (tstamp 57793280)
(at 64.135 51.689 270)
(fp_text reference G*** (at 0 0 270) (layer B.SilkS) hide
(effects (font (thickness 0.3)) (justify mirror))
Initial commit - Full schematic - Partially placed board
2016-06-26 00:26:23 +02:00
)
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(fp_text value LOGO (at 0.75 0 270) (layer B.SilkS) hide
(effects (font (thickness 0.3)) (justify mirror))
Pimped silkscreen a little
2016-07-03 17:50:25 +02:00
)
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(fp_poly (pts (xy 8.515242 0.841711) (xy 8.605944 0.839687) (xy 8.664926 0.836703) (xy 8.680194 0.8349)
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)
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(module Connect:1pin (layer F.Cu) (tedit 57D1BFB0) (tstamp 57D1B8BC)
(at 28.194 57.277)
(descr "module 1 pin (ou trou mecanique de percage)")
(tags DEV)
(fp_text reference 1pin (at 0 -3.048) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value VAL** (at 0 2.794) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_circle (center 0 0) (end 0 -2.286) (layer F.SilkS) (width 0.15))
(pad 1 thru_hole circle (at 0 0) (size 5 5) (drill 3.2) (layers *.Cu *.Mask F.SilkS)
(net 2 GND) (zone_connect 2))
)
(module Resistors_SMD:R_0603_HandSoldering (layer F.Cu) (tedit 57D1C93E) (tstamp 57CF3804)
(at 63.881 45.931 270)
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /575B1260/57CDFED1)
(attr smd)
(fp_text reference R309 (at -3.894 0.254 270) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 10k (at 0 1.9 270) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -2 -0.8) (end 2 -0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end -2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 2 -0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 0.5 0.675) (end -0.5 0.675) (layer F.SilkS) (width 0.15))
(fp_line (start -0.5 -0.675) (end 0.5 -0.675) (layer F.SilkS) (width 0.15))
(pad 1 smd rect (at -1.1 0 270) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
(net 52 "Net-(R309-Pad1)"))
(pad 2 smd rect (at 1.1 0 270) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
(net 48 /Mikrocontroller/LOAD_on))
(model Resistors_SMD/R_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Connect:1pin (layer F.Cu) (tedit 57D1BFB5) (tstamp 57D077DB)
(at 63.5 67.183)
(descr "module 1 pin (ou trou mecanique de percage)")
(tags DEV)
(fp_text reference 1pin (at 0 -3.048) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value VAL** (at 0 2.794) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_circle (center 0 0) (end 0 -2.286) (layer F.SilkS) (width 0.15))
(pad 1 thru_hole circle (at 0 0) (size 5 5) (drill 3.2) (layers *.Cu *.Mask F.SilkS)
(net 2 GND) (zone_connect 2))
)
(module Capacitors_SMD:C_0805_HandSoldering (layer B.Cu) (tedit 57743424) (tstamp 576C3E1E)
(at 38.862 62.23 270)
(descr "Capacitor SMD 0805, hand soldering")
(tags "capacitor 0805")
(path /575C889D)
(attr smd)
(fp_text reference C101 (at 0 2.1 270) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 10u (at 0 -2.1 270) (layer B.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -2.3 1) (end 2.3 1) (layer B.CrtYd) (width 0.05))
(fp_line (start -2.3 -1) (end 2.3 -1) (layer B.CrtYd) (width 0.05))
(fp_line (start -2.3 1) (end -2.3 -1) (layer B.CrtYd) (width 0.05))
(fp_line (start 2.3 1) (end 2.3 -1) (layer B.CrtYd) (width 0.05))
(fp_line (start 0.5 0.85) (end -0.5 0.85) (layer B.SilkS) (width 0.15))
(fp_line (start -0.5 -0.85) (end 0.5 -0.85) (layer B.SilkS) (width 0.15))
(pad 1 smd rect (at -1.25 0 270) (size 1.5 1.25) (layers B.Cu B.Paste B.Mask)
(net 1 +BATT))
(pad 2 smd rect (at 1.25 0 270) (size 1.5 1.25) (layers B.Cu B.Paste B.Mask)
(net 2 GND))
(model Capacitors_SMD/C_0805_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0805_HandSoldering (layer B.Cu) (tedit 5774341A) (tstamp 576C3E2A)
(at 49.51 56.515)
(descr "Capacitor SMD 0805, hand soldering")
(tags "capacitor 0805")
(path /5761FA3A)
(attr smd)
(fp_text reference C103 (at 0.02 -1.778) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 10u (at 0 -2.1) (layer B.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -2.3 1) (end 2.3 1) (layer B.CrtYd) (width 0.05))
(fp_line (start -2.3 -1) (end 2.3 -1) (layer B.CrtYd) (width 0.05))
(fp_line (start -2.3 1) (end -2.3 -1) (layer B.CrtYd) (width 0.05))
(fp_line (start 2.3 1) (end 2.3 -1) (layer B.CrtYd) (width 0.05))
(fp_line (start 0.5 0.85) (end -0.5 0.85) (layer B.SilkS) (width 0.15))
(fp_line (start -0.5 -0.85) (end 0.5 -0.85) (layer B.SilkS) (width 0.15))
(pad 1 smd rect (at -1.25 0) (size 1.5 1.25) (layers B.Cu B.Paste B.Mask)
(net 1 +BATT))
(pad 2 smd rect (at 1.25 0) (size 1.5 1.25) (layers B.Cu B.Paste B.Mask)
(net 2 GND))
(model Capacitors_SMD/C_0805_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer B.Cu) (tedit 577433F6) (tstamp 576C3E3C)
(at 46 44.68 90)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /5761A543/5761C5EC)
(attr smd)
(fp_text reference C201 (at 0 1.9 90) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 22pF (at 0 -1.9 90) (layer B.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end -1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.85 0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -0.35 0.6) (end 0.35 0.6) (layer B.SilkS) (width 0.15))
(fp_line (start 0.35 -0.6) (end -0.35 -0.6) (layer B.SilkS) (width 0.15))
(pad 1 smd rect (at -0.95 0 90) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
(net 6 "Net-(C201-Pad1)"))
(pad 2 smd rect (at 0.95 0 90) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
(net 2 GND))
(model Capacitors_SMD/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer B.Cu) (tedit 5774341F) (tstamp 576C3E42)
(at 46 55.78 270)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /5761A543/5761C689)
(attr smd)
(fp_text reference C202 (at 3.656 0.026 270) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 22pF (at 0 -1.9 270) (layer B.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end -1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.85 0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -0.35 0.6) (end 0.35 0.6) (layer B.SilkS) (width 0.15))
(fp_line (start 0.35 -0.6) (end -0.35 -0.6) (layer B.SilkS) (width 0.15))
(pad 1 smd rect (at -0.95 0 270) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
(net 7 "Net-(C202-Pad1)"))
(pad 2 smd rect (at 0.95 0 270) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
(net 2 GND))
(model Capacitors_SMD/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer F.Cu) (tedit 577432F4) (tstamp 576C3E48)
(at 51 45.93 90)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /5761A543/5761AD6C)
(attr smd)
(fp_text reference C203 (at -0.552 -1.216 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 100nF (at 3.385 -0.2 90) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end -1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.85 -0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.15))
(fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.15))
(pad 1 smd rect (at -0.95 0 90) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 5 +3V3))
(pad 2 smd rect (at 0.95 0 90) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 2 GND))
(model Capacitors_SMD/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer F.Cu) (tedit 57743344) (tstamp 576C3E4E)
(at 61.45 56.48 180)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /5761A543/5761ADD1)
(attr smd)
(fp_text reference C204 (at -2.177 1.489 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 100nF (at 0 1.9 180) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end -1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.85 -0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.15))
(fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.15))
(pad 1 smd rect (at -0.95 0 180) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 5 +3V3))
(pad 2 smd rect (at 0.95 0 180) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 2 GND))
(model Capacitors_SMD/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer B.Cu) (tedit 57743416) (tstamp 576C3E54)
(at 54.7 53.48)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /5761A543/5761ADF4)
(attr smd)
(fp_text reference C205 (at 0 1.9) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 100nF (at 0 -1.9) (layer B.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end -1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.85 0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -0.35 0.6) (end 0.35 0.6) (layer B.SilkS) (width 0.15))
(fp_line (start 0.35 -0.6) (end -0.35 -0.6) (layer B.SilkS) (width 0.15))
(pad 1 smd rect (at -0.95 0) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
(net 5 +3V3))
(pad 2 smd rect (at 0.95 0) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
(net 2 GND))
(model Capacitors_SMD/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0805_HandSoldering (layer B.Cu) (tedit 577433CB) (tstamp 576C3E60)
(at 62.25 26.67 180)
(descr "Capacitor SMD 0805, hand soldering")
(tags "capacitor 0805")
(path /575B1260/575B40E6)
(attr smd)
(fp_text reference C302 (at 4.338 0 180) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 22uF (at 0 -2.1 180) (layer B.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -2.3 1) (end 2.3 1) (layer B.CrtYd) (width 0.05))
(fp_line (start -2.3 -1) (end 2.3 -1) (layer B.CrtYd) (width 0.05))
(fp_line (start -2.3 1) (end -2.3 -1) (layer B.CrtYd) (width 0.05))
(fp_line (start 2.3 1) (end 2.3 -1) (layer B.CrtYd) (width 0.05))
(fp_line (start 0.5 0.85) (end -0.5 0.85) (layer B.SilkS) (width 0.15))
(fp_line (start -0.5 -0.85) (end 0.5 -0.85) (layer B.SilkS) (width 0.15))
(pad 1 smd rect (at -1.25 0 180) (size 1.5 1.25) (layers B.Cu B.Paste B.Mask)
(net 8 "Net-(C302-Pad1)"))
(pad 2 smd rect (at 1.25 0 180) (size 1.5 1.25) (layers B.Cu B.Paste B.Mask)
(net 9 "Net-(C302-Pad2)"))
(model Capacitors_SMD/C_0805_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_Elko_ThroughHole:Elko_vert_25x12.5mm_RM5 (layer F.Cu) (tedit 577432FE) (tstamp 576C3E6C)
(at 36.195 55.245 90)
(descr "Electrolytic Capacitor, vertical, diameter 12,5mm, RM 5mm")
(tags "Electrolytic Capacitor, vertical, diameter 12,5mm, RM 5mm, Elko, Electrolytkondensator, Kondensator gepolt, Durchmesser 12,5mm")
(path /575B1260/575B159B)
(fp_text reference C304 (at 2.667 -4.572 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 470uF (at 2.54 7.62 90) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -1.016 -3.556) (end -1.016 -2.54) (layer F.SilkS) (width 0.15))
(fp_line (start -1.524 -3.048) (end -0.508 -3.048) (layer F.SilkS) (width 0.15))
(fp_line (start -1.016 -3.556) (end -1.016 -2.54) (layer F.Cu) (width 0.15))
(fp_line (start -1.524 -3.048) (end -0.508 -3.048) (layer F.Cu) (width 0.15))
(fp_circle (center 2.54 0) (end 8.89 0) (layer F.SilkS) (width 0.15))
(pad 2 thru_hole circle (at 5.08 0 90) (size 2.99974 2.99974) (drill 1.19888) (layers *.Cu *.Mask F.SilkS)
(net 11 "/Power Converter/Bat-"))
(pad 1 thru_hole circle (at 0 0 90) (size 2.99974 2.99974) (drill 1.19888) (layers *.Cu *.Mask F.SilkS)
(net 1 +BATT))
(model Capacitors_Elko_ThroughHole/Elko_vert_25x12.5mm_RM5.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module TO-SMD:TO-277 (layer B.Cu) (tedit 576C373F) (tstamp 576C3E79)
(at 61 32.494594 90)
(path /575B1260/576C4566)
(fp_text reference D302 (at 1.506594 -3.469 90) (layer B.SilkS)
(effects (font (size 1.5 1.5) (thickness 0.15)) (justify mirror))
)
(fp_text value SCH-TO-277 (at 0 3.81 90) (layer B.Fab)
(effects (font (size 1.5 1.5) (thickness 0.15)) (justify mirror))
)
(pad 3 smd rect (at 1.4 0 90) (size 5.5 4.2) (layers B.Cu B.Paste B.Mask)
(net 9 "Net-(C302-Pad2)"))
(pad 1 smd rect (at -2.9 -0.985 90) (size 1.45 1.5) (layers B.Cu B.Paste B.Mask)
(net 2 GND))
(pad 2 smd rect (at -2.9 0.985 90) (size 1.45 1.5) (layers B.Cu B.Paste B.Mask)
(net 2 GND))
)
(module PowerInductors:LPV2023-101KL (layer F.Cu) (tedit 576C3AC7) (tstamp 576C3E7F)
(at 28.705 37.465)
(path /575B1260/575B1760)
(fp_text reference L301 (at 0 2) (layer F.SilkS)
(effects (font (size 1.5 1.5) (thickness 0.15)))
)
(fp_text value 100uH (at 0 -3) (layer F.Fab)
(effects (font (size 1.5 1.5) (thickness 0.15)))
)
(fp_circle (center 0 0) (end 10 0) (layer F.SilkS) (width 0.15))
(pad 1 thru_hole circle (at 7.75 0) (size 2.5 2.5) (drill 1.2) (layers *.Cu *.Mask F.SilkS)
(net 10 "/Power Converter/VInDirect"))
(pad 2 thru_hole circle (at -7.75 0) (size 2.5 2.5) (drill 1.2) (layers *.Cu *.Mask F.SilkS)
(net 12 "Net-(D301-Pad1)"))
)
(module PowerInductors:CustomCore_27x20.5mm (layer F.Cu) (tedit 576C3CF2) (tstamp 576C3E85)
(at 54.048306 31.094594 90)
(path /575B1260/575B1308)
(fp_text reference L302 (at 0 -5 90) (layer F.SilkS)
(effects (font (size 1.5 1.5) (thickness 0.15)))
)
(fp_text value 1mH (at 0 5 90) (layer F.Fab)
(effects (font (size 1.5 1.5) (thickness 0.15)))
)
(fp_line (start -13.5 -10.25) (end -13.5 10.25) (layer F.SilkS) (width 0.15))
(fp_line (start 13.5 -10.25) (end -13.5 -10.25) (layer F.SilkS) (width 0.15))
(fp_line (start 13.5 10.25) (end 13.5 -10.25) (layer F.SilkS) (width 0.15))
(fp_line (start -13.5 10.25) (end 13.5 10.25) (layer F.SilkS) (width 0.15))
(pad 1 thru_hole circle (at 0 -12 90) (size 2.5 2.5) (drill 1.2) (layers *.Cu *.Mask F.SilkS)
(net 1 +BATT))
(pad 2 thru_hole circle (at 0 12 90) (size 2.5 2.5) (drill 1.2) (layers *.Cu *.Mask F.SilkS)
(net 9 "Net-(C302-Pad2)"))
)
(module Connect:bornier2 (layer F.Cu) (tedit 57743221) (tstamp 576C3E8B)
(at 21.336 21.59 90)
(descr "Bornier d'alimentation 2 pins")
(tags DEV)
(path /5761A72F)
(fp_text reference P101 (at 0 -5.08 90) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value CONN_PANEL (at -0.13 4.551 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 5.08 2.54) (end -5.08 2.54) (layer F.SilkS) (width 0.15))
(fp_line (start 5.08 3.81) (end 5.08 -3.81) (layer F.SilkS) (width 0.15))
(fp_line (start 5.08 -3.81) (end -5.08 -3.81) (layer F.SilkS) (width 0.15))
(fp_line (start -5.08 -3.81) (end -5.08 3.81) (layer F.SilkS) (width 0.15))
(fp_line (start -5.08 3.81) (end 5.08 3.81) (layer F.SilkS) (width 0.15))
(pad 1 thru_hole rect (at -2.54 0 90) (size 2.54 2.54) (drill 1.524) (layers *.Cu *.Mask F.SilkS)
(net 13 "/Power Converter/Vpanel"))
(pad 2 thru_hole circle (at 2.54 0 90) (size 2.54 2.54) (drill 1.524) (layers *.Cu *.Mask F.SilkS)
(net 2 GND))
(model Connect/bornier2.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Connect:bornier2 (layer F.Cu) (tedit 57743230) (tstamp 576C3E91)
(at 21.59 53.34 90)
(descr "Bornier d'alimentation 2 pins")
(tags DEV)
(path /575C825E)
(fp_text reference P102 (at 0 -5.08 90) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value CONN_BAT (at 2.286 4.699 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 5.08 2.54) (end -5.08 2.54) (layer F.SilkS) (width 0.15))
(fp_line (start 5.08 3.81) (end 5.08 -3.81) (layer F.SilkS) (width 0.15))
(fp_line (start 5.08 -3.81) (end -5.08 -3.81) (layer F.SilkS) (width 0.15))
(fp_line (start -5.08 -3.81) (end -5.08 3.81) (layer F.SilkS) (width 0.15))
(fp_line (start -5.08 3.81) (end 5.08 3.81) (layer F.SilkS) (width 0.15))
(pad 1 thru_hole rect (at -2.54 0 90) (size 2.54 2.54) (drill 1.524) (layers *.Cu *.Mask F.SilkS)
(net 1 +BATT))
(pad 2 thru_hole circle (at 2.54 0 90) (size 2.54 2.54) (drill 1.524) (layers *.Cu *.Mask F.SilkS)
(net 11 "/Power Converter/Bat-"))
(model Connect/bornier2.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Connect:bornier2 (layer F.Cu) (tedit 57743234) (tstamp 576C3E97)
(at 21.59 64.135 90)
(descr "Bornier d'alimentation 2 pins")
(tags DEV)
(path /5769D6B5)
(fp_text reference P103 (at 0 -5.08 90) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value CONN_LOAD (at 0.635 4.572 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 5.08 2.54) (end -5.08 2.54) (layer F.SilkS) (width 0.15))
(fp_line (start 5.08 3.81) (end 5.08 -3.81) (layer F.SilkS) (width 0.15))
(fp_line (start 5.08 -3.81) (end -5.08 -3.81) (layer F.SilkS) (width 0.15))
(fp_line (start -5.08 -3.81) (end -5.08 3.81) (layer F.SilkS) (width 0.15))
(fp_line (start -5.08 3.81) (end 5.08 3.81) (layer F.SilkS) (width 0.15))
(pad 1 thru_hole rect (at -2.54 0 90) (size 2.54 2.54) (drill 1.524) (layers *.Cu *.Mask F.SilkS)
(net 1 +BATT))
(pad 2 thru_hole circle (at 2.54 0 90) (size 2.54 2.54) (drill 1.524) (layers *.Cu *.Mask F.SilkS)
(net 14 "/Power Converter/Load-"))
(model Connect/bornier2.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Pin_Arrays:pin_array_1x03 (layer F.Cu) (tedit 0) (tstamp 576C3E9E)
(at 68.453 50.8 90)
(descr "Connecteur 3 pins")
(tags "CONN DEV")
(path /5761A543/5761CA19)
(fp_text reference P201 (at 0 -2.032 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value CONN_UART (at 0 -2.159 90) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -3.81 1.27) (end -3.81 -1.27) (layer F.SilkS) (width 0.15))
(fp_line (start -3.81 -1.27) (end 3.81 -1.27) (layer F.SilkS) (width 0.15))
(fp_line (start 3.81 -1.27) (end 3.81 1.27) (layer F.SilkS) (width 0.15))
(fp_line (start 3.81 1.27) (end -3.81 1.27) (layer F.SilkS) (width 0.15))
(fp_line (start -1.27 -1.27) (end -1.27 1.27) (layer F.SilkS) (width 0.15))
(pad 1 thru_hole rect (at -2.54 0 90) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
(net 2 GND))
(pad 2 thru_hole circle (at 0 0 90) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
(net 16 /Mikrocontroller/UART_RX))
(pad 3 thru_hole circle (at 2.54 0 90) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
(net 15 /Mikrocontroller/UART_TX))
(model Pin_Arrays/pin_array_1x03.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Pin_Arrays:pin_array_1x06 (layer F.Cu) (tedit 0) (tstamp 576C3EA8)
(at 68.453 64.77 90)
(descr "Connecteur 6 pins")
(tags "CONN DEV")
(path /5761A543/5761B5EA)
(fp_text reference P202 (at 1.524 -2.159 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value CONN_SWD (at 0 2.159 90) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -7.62 1.27) (end -7.62 -1.27) (layer F.SilkS) (width 0.15))
(fp_line (start -7.62 -1.27) (end 7.62 -1.27) (layer F.SilkS) (width 0.15))
(fp_line (start 7.62 -1.27) (end 7.62 1.27) (layer F.SilkS) (width 0.15))
(fp_line (start 7.62 1.27) (end -7.62 1.27) (layer F.SilkS) (width 0.15))
(fp_line (start -5.08 1.27) (end -5.08 -1.27) (layer F.SilkS) (width 0.15))
(pad 1 thru_hole rect (at -6.35 0 90) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
(net 5 +3V3))
(pad 2 thru_hole circle (at -3.81 0 90) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
(net 17 /Mikrocontroller/SWCLK))
(pad 3 thru_hole circle (at -1.27 0 90) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
(net 2 GND))
(pad 4 thru_hole circle (at 1.27 0 90) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
(net 18 /Mikrocontroller/SWDIO))
(pad 5 thru_hole circle (at 3.81 0 90) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
(net 19 /Mikrocontroller/RST_N))
(pad 6 thru_hole circle (at 6.35 0 90) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
(net 20 "Net-(P202-Pad6)"))
(model Pin_Arrays/pin_array_1x06.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Pin_Headers:Pin_Header_Straight_1x16 (layer F.Cu) (tedit 0) (tstamp 576C3EBC)
(at 39.35 70.98)
(descr "Through hole pin header")
(tags "pin header")
(path /5761A543/5769C283)
(fp_text reference P203 (at 22.499 0.013) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value CONN_DISP (at 0 0) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -17.78 1.27) (end 20.32 1.27) (layer F.SilkS) (width 0.15))
(fp_line (start 20.32 1.27) (end 20.32 -1.27) (layer F.SilkS) (width 0.15))
(fp_line (start 20.32 -1.27) (end -17.78 -1.27) (layer F.SilkS) (width 0.15))
(fp_line (start -20.32 -1.27) (end -17.78 -1.27) (layer F.SilkS) (width 0.15))
(fp_line (start -17.78 -1.27) (end -17.78 1.27) (layer F.SilkS) (width 0.15))
(fp_line (start -20.32 -1.27) (end -20.32 1.27) (layer F.SilkS) (width 0.15))
(fp_line (start -20.32 1.27) (end -17.78 1.27) (layer F.SilkS) (width 0.15))
(pad 1 thru_hole rect (at -19.05 0) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
(net 2 GND))
(pad 2 thru_hole oval (at -16.51 0) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
(net 4 +5V))
(pad 3 thru_hole oval (at -13.97 0) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
(net 21 /Mikrocontroller/DISP_CONTRAST))
(pad 4 thru_hole oval (at -11.43 0) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
(net 22 /Mikrocontroller/DISP_RS))
(pad 5 thru_hole oval (at -8.89 0) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
(net 23 /Mikrocontroller/DISP_RW))
(pad 6 thru_hole oval (at -6.35 0) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
(net 24 /Mikrocontroller/DISP_E))
(pad 7 thru_hole oval (at -3.81 0) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
(net 25 "Net-(P203-Pad7)"))
(pad 8 thru_hole oval (at -1.27 0) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
(net 26 "Net-(P203-Pad8)"))
(pad 9 thru_hole oval (at 1.27 0) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
(net 27 "Net-(P203-Pad9)"))
(pad 10 thru_hole oval (at 3.81 0) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
(net 28 "Net-(P203-Pad10)"))
(pad 11 thru_hole oval (at 6.35 0) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
(net 29 /Mikrocontroller/DISP_D0))
(pad 12 thru_hole oval (at 8.89 0) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
(net 30 /Mikrocontroller/DISP_D1))
(pad 13 thru_hole oval (at 11.43 0) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
(net 31 /Mikrocontroller/DISP_D2))
(pad 14 thru_hole oval (at 13.97 0) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
(net 32 /Mikrocontroller/DISP_D3))
(pad 15 thru_hole oval (at 16.51 0) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
(net 33 "Net-(P203-Pad15)"))
(pad 16 thru_hole oval (at 19.05 0) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
(net 34 "Net-(P203-Pad16)"))
(model Pin_Headers/Pin_Header_Straight_1x16.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module SMD_Packages:SOT-23 (layer B.Cu) (tedit 577433FF) (tstamp 576C3EC3)
(at 54.9275 33.82518 180)
(tags SOT23)
(path /575B1260/576AFC6F)
(fp_text reference Q301 (at 1.8415 2.71018 450) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value Q_NPN_BEC (at 0.0635 0 180) (layer B.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_circle (center -1.17602 -0.35052) (end -1.30048 -0.44958) (layer B.SilkS) (width 0.15))
(fp_line (start 1.27 0.508) (end 1.27 -0.508) (layer B.SilkS) (width 0.15))
(fp_line (start -1.3335 0.508) (end -1.3335 -0.508) (layer B.SilkS) (width 0.15))
(fp_line (start 1.27 -0.508) (end -1.3335 -0.508) (layer B.SilkS) (width 0.15))
(fp_line (start -1.3335 0.508) (end 1.27 0.508) (layer B.SilkS) (width 0.15))
(pad 3 smd rect (at 0 1.09982 180) (size 0.8001 1.00076) (layers B.Cu B.Paste B.Mask)
(net 9 "Net-(C302-Pad2)"))
(pad 2 smd rect (at 0.9525 -1.09982 180) (size 0.8001 1.00076) (layers B.Cu B.Paste B.Mask)
(net 2 GND))
(pad 1 smd rect (at -0.9525 -1.09982 180) (size 0.8001 1.00076) (layers B.Cu B.Paste B.Mask)
(net 35 "Net-(Q301-Pad1)"))
(model SMD_Packages/SOT-23.wrl
(at (xyz 0 0 0))
(scale (xyz 0.4 0.4 0.4))
(rotate (xyz 0 0 180))
)
)
(module SMD_Packages:DPAK-2 (layer B.Cu) (tedit 577433BD) (tstamp 576C3ECA)
(at 53.5 21.286 270)
(descr "MOS boitier DPACK G-D-S")
(tags "CMD DPACK")
(path /575B1260/575B16B6)
(attr smd)
(fp_text reference Q302 (at 0 10.414 270) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value Q_NMOS_GDS (at 0 2.413 270) (layer B.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start 1.397 1.524) (end 1.397 -1.651) (layer B.SilkS) (width 0.15))
(fp_line (start 1.397 -1.651) (end 3.175 -1.651) (layer B.SilkS) (width 0.15))
(fp_line (start 3.175 -1.651) (end 3.175 1.524) (layer B.SilkS) (width 0.15))
(fp_line (start -3.175 1.524) (end -3.175 -1.651) (layer B.SilkS) (width 0.15))
(fp_line (start -3.175 -1.651) (end -1.397 -1.651) (layer B.SilkS) (width 0.15))
(fp_line (start -1.397 -1.651) (end -1.397 1.524) (layer B.SilkS) (width 0.15))
(fp_line (start 3.429 7.62) (end 3.429 1.524) (layer B.SilkS) (width 0.15))
(fp_line (start 3.429 1.524) (end -3.429 1.524) (layer B.SilkS) (width 0.15))
(fp_line (start -3.429 1.524) (end -3.429 9.398) (layer B.SilkS) (width 0.15))
(fp_line (start -3.429 9.525) (end 3.429 9.525) (layer B.SilkS) (width 0.15))
(fp_line (start 3.429 9.398) (end 3.429 7.62) (layer B.SilkS) (width 0.15))
(pad 1 smd rect (at -2.286 0 270) (size 1.651 3.048) (layers B.Cu B.Paste B.Mask)
(net 36 "Net-(Q302-Pad1)"))
(pad 2 smd rect (at 0 6.35 270) (size 6.096 6.096) (layers B.Cu B.Paste B.Mask)
(net 10 "/Power Converter/VInDirect"))
(pad 3 smd rect (at 2.286 0 270) (size 1.651 3.048) (layers B.Cu B.Paste B.Mask)
(net 9 "Net-(C302-Pad2)"))
(model SMD_Packages/DPAK-2.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module SMD_Packages:DPAK-2 (layer F.Cu) (tedit 5774326C) (tstamp 576C3ED1)
(at 36.83 63.5 90)
(descr "MOS boitier DPACK G-D-S")
(tags "CMD DPACK")
(path /575B1260/5769CC83)
(attr smd)
(fp_text reference Q303 (at 0.127 -2.286 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Q_NMOS_GDS (at 0 -2.413 90) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.397 -1.524) (end 1.397 1.651) (layer F.SilkS) (width 0.15))
(fp_line (start 1.397 1.651) (end 3.175 1.651) (layer F.SilkS) (width 0.15))
(fp_line (start 3.175 1.651) (end 3.175 -1.524) (layer F.SilkS) (width 0.15))
(fp_line (start -3.175 -1.524) (end -3.175 1.651) (layer F.SilkS) (width 0.15))
(fp_line (start -3.175 1.651) (end -1.397 1.651) (layer F.SilkS) (width 0.15))
(fp_line (start -1.397 1.651) (end -1.397 -1.524) (layer F.SilkS) (width 0.15))
(fp_line (start 3.429 -7.62) (end 3.429 -1.524) (layer F.SilkS) (width 0.15))
(fp_line (start 3.429 -1.524) (end -3.429 -1.524) (layer F.SilkS) (width 0.15))
(fp_line (start -3.429 -1.524) (end -3.429 -9.398) (layer F.SilkS) (width 0.15))
(fp_line (start -3.429 -9.525) (end 3.429 -9.525) (layer F.SilkS) (width 0.15))
(fp_line (start 3.429 -9.398) (end 3.429 -7.62) (layer F.SilkS) (width 0.15))
(pad 1 smd rect (at -2.286 0 90) (size 1.651 3.048) (layers F.Cu F.Paste F.Mask)
(net 37 "/Power Converter/LoadDrive"))
(pad 2 smd rect (at 0 -6.35 90) (size 6.096 6.096) (layers F.Cu F.Paste F.Mask)
(net 14 "/Power Converter/Load-"))
(pad 3 smd rect (at 2.286 0 90) (size 1.651 3.048) (layers F.Cu F.Paste F.Mask)
(net 11 "/Power Converter/Bat-"))
(model SMD_Packages/DPAK-2.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_0603_HandSoldering (layer B.Cu) (tedit 5774340D) (tstamp 576C3ED7)
(at 55.245 50.335 90)
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /5761A543/5761B9EF)
(attr smd)
(fp_text reference R201 (at 0 1.9 90) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 10k (at 0 -1.9 90) (layer B.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -2 0.8) (end 2 0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end 2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end -2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start 2 0.8) (end 2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start 0.5 -0.675) (end -0.5 -0.675) (layer B.SilkS) (width 0.15))
(fp_line (start -0.5 0.675) (end 0.5 0.675) (layer B.SilkS) (width 0.15))
(pad 1 smd rect (at -1.1 0 90) (size 1.2 0.9) (layers B.Cu B.Paste B.Mask)
(net 5 +3V3))
(pad 2 smd rect (at 1.1 0 90) (size 1.2 0.9) (layers B.Cu B.Paste B.Mask)
(net 19 /Mikrocontroller/RST_N))
(model Resistors_SMD/R_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_0603_HandSoldering (layer B.Cu) (tedit 57743409) (tstamp 576C3EDD)
(at 52.15 46.48 180)
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /5761A543/5761C479)
(attr smd)
(fp_text reference R202 (at 0 1.9 180) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 10k (at 0 -1.9 180) (layer B.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -2 0.8) (end 2 0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end 2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end -2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start 2 0.8) (end 2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start 0.5 -0.675) (end -0.5 -0.675) (layer B.SilkS) (width 0.15))
(fp_line (start -0.5 0.675) (end 0.5 0.675) (layer B.SilkS) (width 0.15))
(pad 1 smd rect (at -1.1 0 180) (size 1.2 0.9) (layers B.Cu B.Paste B.Mask)
(net 38 "Net-(R202-Pad1)"))
(pad 2 smd rect (at 1.1 0 180) (size 1.2 0.9) (layers B.Cu B.Paste B.Mask)
(net 2 GND))
(model Resistors_SMD/R_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_0603_HandSoldering (layer F.Cu) (tedit 57743341) (tstamp 576C3EE3)
(at 28.405 67.945 180)
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /5761A543/5769B472)
(attr smd)
(fp_text reference R203 (at 0.084 -1.397 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value N.B. (at -0.17 1.524 180) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -2 -0.8) (end 2 -0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end -2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 2 -0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 0.5 0.675) (end -0.5 0.675) (layer F.SilkS) (width 0.15))
(fp_line (start -0.5 -0.675) (end 0.5 -0.675) (layer F.SilkS) (width 0.15))
(pad 1 smd rect (at -1.1 0 180) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
(net 21 /Mikrocontroller/DISP_CONTRAST))
(pad 2 smd rect (at 1.1 0 180) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
(net 4 +5V))
(model Resistors_SMD/R_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_0603_HandSoldering (layer F.Cu) (tedit 57743335) (tstamp 576C3EE9)
(at 32.85 67.945 180)
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /5761A543/5769B5EC)
(attr smd)
(fp_text reference R204 (at 0 -1.397 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 470 (at 0 1.9 180) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -2 -0.8) (end 2 -0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end -2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 2 -0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 0.5 0.675) (end -0.5 0.675) (layer F.SilkS) (width 0.15))
(fp_line (start -0.5 -0.675) (end 0.5 -0.675) (layer F.SilkS) (width 0.15))
(pad 1 smd rect (at -1.1 0 180) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
(net 2 GND))
(pad 2 smd rect (at 1.1 0 180) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
(net 21 /Mikrocontroller/DISP_CONTRAST))
(model Resistors_SMD/R_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_0603_HandSoldering (layer B.Cu) (tedit 57743403) (tstamp 576C3EEF)
(at 55.88 38.565 270)
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /575B1260/575DD02D)
(attr smd)
(fp_text reference R301 (at 0 1.9 270) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 1k (at 0 -1.9 270) (layer B.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -2 0.8) (end 2 0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end 2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end -2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start 2 0.8) (end 2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start 0.5 -0.675) (end -0.5 -0.675) (layer B.SilkS) (width 0.15))
(fp_line (start -0.5 0.675) (end 0.5 0.675) (layer B.SilkS) (width 0.15))
(pad 1 smd rect (at -1.1 0 270) (size 1.2 0.9) (layers B.Cu B.Paste B.Mask)
(net 35 "Net-(Q301-Pad1)"))
(pad 2 smd rect (at 1.1 0 270) (size 1.2 0.9) (layers B.Cu B.Paste B.Mask)
(net 39 /Mikrocontroller/BootstrapPulse))
(model Resistors_SMD/R_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_1206_HandSoldering (layer B.Cu) (tedit 577433F3) (tstamp 576C3EF5)
(at 36.195 43.91 90)
(descr "Resistor SMD 1206, hand soldering")
(tags "resistor 1206")
(path /575B1260/575B14F1)
(attr smd)
(fp_text reference R302 (at 0 2.3 90) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value R010 (at 0 -2.3 90) (layer B.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -3.3 1.2) (end 3.3 1.2) (layer B.CrtYd) (width 0.05))
(fp_line (start -3.3 -1.2) (end 3.3 -1.2) (layer B.CrtYd) (width 0.05))
(fp_line (start -3.3 1.2) (end -3.3 -1.2) (layer B.CrtYd) (width 0.05))
(fp_line (start 3.3 1.2) (end 3.3 -1.2) (layer B.CrtYd) (width 0.05))
(fp_line (start 1 -1.075) (end -1 -1.075) (layer B.SilkS) (width 0.15))
(fp_line (start -1 1.075) (end 1 1.075) (layer B.SilkS) (width 0.15))
(pad 1 smd rect (at -2 0 90) (size 2 1.7) (layers B.Cu B.Paste B.Mask)
(net 11 "/Power Converter/Bat-"))
(pad 2 smd rect (at 2 0 90) (size 2 1.7) (layers B.Cu B.Paste B.Mask)
(net 2 GND))
(model Resistors_SMD/R_1206_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_0603_HandSoldering (layer B.Cu) (tedit 577433C0) (tstamp 576C3EFB)
(at 37.979466 24.681678 180)
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /575B1260/575B25FD)
(attr smd)
(fp_text reference R303 (at 0.006466 -3.004322 180) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 100k (at 0 -1.9 180) (layer B.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -2 0.8) (end 2 0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end 2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end -2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start 2 0.8) (end 2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start 0.5 -0.675) (end -0.5 -0.675) (layer B.SilkS) (width 0.15))
(fp_line (start -0.5 0.675) (end 0.5 0.675) (layer B.SilkS) (width 0.15))
(pad 1 smd rect (at -1.1 0 180) (size 1.2 0.9) (layers B.Cu B.Paste B.Mask)
(net 10 "/Power Converter/VInDirect"))
(pad 2 smd rect (at 1.1 0 180) (size 1.2 0.9) (layers B.Cu B.Paste B.Mask)
(net 40 /Mikrocontroller/VInSense))
(model Resistors_SMD/R_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_0603_HandSoldering (layer B.Cu) (tedit 577433C3) (tstamp 576C3F01)
(at 33.704466 24.681678 180)
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /575B1260/575B26C0)
(attr smd)
(fp_text reference R304 (at 0.049466 -3.004322 180) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 10k (at 0 -1.9 180) (layer B.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -2 0.8) (end 2 0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end 2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end -2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start 2 0.8) (end 2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start 0.5 -0.675) (end -0.5 -0.675) (layer B.SilkS) (width 0.15))
(fp_line (start -0.5 0.675) (end 0.5 0.675) (layer B.SilkS) (width 0.15))
(pad 1 smd rect (at -1.1 0 180) (size 1.2 0.9) (layers B.Cu B.Paste B.Mask)
(net 40 /Mikrocontroller/VInSense))
(pad 2 smd rect (at 1.1 0 180) (size 1.2 0.9) (layers B.Cu B.Paste B.Mask)
(net 2 GND))
(model Resistors_SMD/R_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_0603_HandSoldering (layer B.Cu) (tedit 57743428) (tstamp 576C3F07)
(at 39.924664 54.315222 270)
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /575B1260/575B31F0)
(attr smd)
(fp_text reference R305 (at -5.166222 -0.080336 270) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 100k (at 0 -1.9 270) (layer B.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -2 0.8) (end 2 0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end 2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end -2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start 2 0.8) (end 2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start 0.5 -0.675) (end -0.5 -0.675) (layer B.SilkS) (width 0.15))
(fp_line (start -0.5 0.675) (end 0.5 0.675) (layer B.SilkS) (width 0.15))
(pad 1 smd rect (at -1.1 0 270) (size 1.2 0.9) (layers B.Cu B.Paste B.Mask)
(net 1 +BATT))
(pad 2 smd rect (at 1.1 0 270) (size 1.2 0.9) (layers B.Cu B.Paste B.Mask)
(net 41 /Mikrocontroller/VOutSense))
(model Resistors_SMD/R_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_0603_HandSoldering (layer B.Cu) (tedit 5774342B) (tstamp 576C3F0D)
(at 42 54.38 90)
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /575B1260/575B318A)
(attr smd)
(fp_text reference R306 (at 5.231 0.037 90) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 12k (at 0 -1.9 90) (layer B.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -2 0.8) (end 2 0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end 2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end -2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start 2 0.8) (end 2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start 0.5 -0.675) (end -0.5 -0.675) (layer B.SilkS) (width 0.15))
(fp_line (start -0.5 0.675) (end 0.5 0.675) (layer B.SilkS) (width 0.15))
(pad 1 smd rect (at -1.1 0 90) (size 1.2 0.9) (layers B.Cu B.Paste B.Mask)
(net 41 /Mikrocontroller/VOutSense))
(pad 2 smd rect (at 1.1 0 90) (size 1.2 0.9) (layers B.Cu B.Paste B.Mask)
(net 2 GND))
(model Resistors_SMD/R_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_0603_HandSoldering (layer B.Cu) (tedit 577433EA) (tstamp 576C3F13)
(at 31.58 38.1 180)
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /575B1260/575B5038)
(attr smd)
(fp_text reference R307 (at 0 1.9 180) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 33k (at 0 -1.9 180) (layer B.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -2 0.8) (end 2 0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end 2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end -2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start 2 0.8) (end 2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start 0.5 -0.675) (end -0.5 -0.675) (layer B.SilkS) (width 0.15))
(fp_line (start -0.5 0.675) (end 0.5 0.675) (layer B.SilkS) (width 0.15))
(pad 1 smd rect (at -1.1 0 180) (size 1.2 0.9) (layers B.Cu B.Paste B.Mask)
(net 42 /Mikrocontroller/CurrentSense))
(pad 2 smd rect (at 1.1 0 180) (size 1.2 0.9) (layers B.Cu B.Paste B.Mask)
(net 43 "Net-(R307-Pad2)"))
(model Resistors_SMD/R_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_0603_HandSoldering (layer B.Cu) (tedit 577433ED) (tstamp 576C3F19)
(at 31.75 43.815)
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /575B1260/575B50AB)
(attr smd)
(fp_text reference R308 (at 0 1.9) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 1k (at 0 -1.9) (layer B.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -2 0.8) (end 2 0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end 2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end -2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start 2 0.8) (end 2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start 0.5 -0.675) (end -0.5 -0.675) (layer B.SilkS) (width 0.15))
(fp_line (start -0.5 0.675) (end 0.5 0.675) (layer B.SilkS) (width 0.15))
(pad 1 smd rect (at -1.1 0) (size 1.2 0.9) (layers B.Cu B.Paste B.Mask)
(net 43 "Net-(R307-Pad2)"))
(pad 2 smd rect (at 1.1 0) (size 1.2 0.9) (layers B.Cu B.Paste B.Mask)
(net 2 GND))
(model Resistors_SMD/R_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Housings_TO-92:TO-92-Free-molded-wide-oval (layer F.Cu) (tedit 57743374) (tstamp 576C3F20)
(at 50.165 59.69 270)
(descr "TO-92 allgemein free molded wide oval drill 0,8mm")
(tags "TO-92 allgemein free molded wide oval drill 0,8mm")
(path /575C88BC)
(fp_text reference U101 (at -2.159 0.127 360) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value LM78L12ACZ (at 2.032 4.191 270) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -1.524 2.413) (end -1.27 2.667) (layer F.SilkS) (width 0.15))
(fp_line (start 1.3589 2.7178) (end 1.2319 2.7813) (layer F.SilkS) (width 0.15))
(fp_line (start 1.4986 -2.6035) (end 1.2446 -2.7432) (layer F.SilkS) (width 0.15))
(fp_line (start 1.2446 -2.7432) (end 1.2446 -2.6924) (layer F.SilkS) (width 0.15))
(fp_line (start 2.6289 1.5367) (end 2.7305 1.3081) (layer F.SilkS) (width 0.15))
(fp_line (start 2.7305 1.3081) (end 2.7559 1.2319) (layer F.SilkS) (width 0.15))
(fp_line (start 2.6543 -1.4605) (end 2.7432 -1.2446) (layer F.SilkS) (width 0.15))
(fp_line (start 2.6035 1.524) (end 2.3495 1.905) (layer F.SilkS) (width 0.15))
(fp_line (start 2.3495 1.905) (end 2.032 2.286) (layer F.SilkS) (width 0.15))
(fp_line (start 2.032 2.286) (end 1.651 2.54) (layer F.SilkS) (width 0.15))
(fp_line (start 1.651 2.54) (end 1.3335 2.7305) (layer F.SilkS) (width 0.15))
(fp_line (start -1.524 -2.413) (end -1.2065 -2.6035) (layer F.SilkS) (width 0.15))
(fp_line (start 1.524 -2.6035) (end 1.7145 -2.4765) (layer F.SilkS) (width 0.15))
(fp_line (start 1.7145 -2.4765) (end 1.9685 -2.286) (layer F.SilkS) (width 0.15))
(fp_line (start 1.9685 -2.286) (end 2.3495 -1.905) (layer F.SilkS) (width 0.15))
(fp_line (start 2.3495 -1.905) (end 2.667 -1.4605) (layer F.SilkS) (width 0.15))
(fp_line (start -1.524 0) (end -1.524 2.413) (layer F.SilkS) (width 0.15))
(fp_line (start -1.524 0) (end -1.524 -2.413) (layer F.SilkS) (width 0.15))
(pad 2 thru_hole oval (at 2.54 0 270) (size 1.99898 1.50114) (drill 0.8001) (layers *.Cu *.Mask F.SilkS)
(net 2 GND))
(pad 1 thru_hole oval (at 0 -2.54 270) (size 1.50114 1.99898) (drill 0.8001) (layers *.Cu *.Mask F.SilkS)
(net 3 +12V))
(pad 3 thru_hole oval (at 0 2.54 270) (size 1.50114 1.99898) (drill 0.8001) (layers *.Cu *.Mask F.SilkS)
(net 1 +BATT))
)
(module Power_Integrations:TO-220 (layer F.Cu) (tedit 0) (tstamp 576C3F27)
(at 42.545 63.5 270)
(descr "Non Isolated JEDEC TO-220 Package")
(tags "Power Integration YN Package")
(path /5761F664)
(fp_text reference U102 (at 0 2.413 270) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value LM7805CT (at 0 -4.318 270) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 4.826 -1.651) (end 4.826 1.778) (layer F.SilkS) (width 0.15))
(fp_line (start -4.826 -1.651) (end -4.826 1.778) (layer F.SilkS) (width 0.15))
(fp_line (start 5.334 -2.794) (end -5.334 -2.794) (layer F.SilkS) (width 0.15))
(fp_line (start 1.778 -1.778) (end 1.778 -3.048) (layer F.SilkS) (width 0.15))
(fp_line (start -1.778 -1.778) (end -1.778 -3.048) (layer F.SilkS) (width 0.15))
(fp_line (start -5.334 -1.651) (end 5.334 -1.651) (layer F.SilkS) (width 0.15))
(fp_line (start 5.334 1.778) (end -5.334 1.778) (layer F.SilkS) (width 0.15))
(fp_line (start -5.334 -3.048) (end -5.334 1.778) (layer F.SilkS) (width 0.15))
(fp_line (start 5.334 -3.048) (end 5.334 1.778) (layer F.SilkS) (width 0.15))
(fp_line (start 5.334 -3.048) (end -5.334 -3.048) (layer F.SilkS) (width 0.15))
(pad 2 thru_hole oval (at 0 0 270) (size 2.032 2.54) (drill 1.143) (layers *.Cu *.Mask F.SilkS)
(net 2 GND))
(pad 3 thru_hole oval (at 2.54 0 270) (size 2.032 2.54) (drill 1.143) (layers *.Cu *.Mask F.SilkS)
(net 4 +5V))
(pad 1 thru_hole oval (at -2.54 0 270) (size 2.032 2.54) (drill 1.143) (layers *.Cu *.Mask F.SilkS)
(net 1 +BATT))
)
(module SMD_Packages:TQFP-32 (layer F.Cu) (tedit 0) (tstamp 576C3F53)
(at 55.7502 51.6618)
(path /5761A543/5761A64E)
(fp_text reference U201 (at 0 -1.27) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value STM32F030K6 (at 1.5268 -7.8468) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 5.0292 2.7686) (end 3.8862 2.7686) (layer F.SilkS) (width 0.15))
(fp_line (start 5.0292 -2.7686) (end 3.9116 -2.7686) (layer F.SilkS) (width 0.15))
(fp_line (start 5.0292 2.7686) (end 5.0292 -2.7686) (layer F.SilkS) (width 0.15))
(fp_line (start 2.794 3.9624) (end 2.794 5.0546) (layer F.SilkS) (width 0.15))
(fp_line (start -2.8194 3.9878) (end -2.8194 5.0546) (layer F.SilkS) (width 0.15))
(fp_line (start -2.8448 5.0546) (end 2.794 5.08) (layer F.SilkS) (width 0.15))
(fp_line (start -2.794 -5.0292) (end 2.7178 -5.0546) (layer F.SilkS) (width 0.15))
(fp_line (start -3.8862 -3.2766) (end -3.8862 3.9116) (layer F.SilkS) (width 0.15))
(fp_line (start 2.7432 -5.0292) (end 2.7432 -3.9878) (layer F.SilkS) (width 0.15))
(fp_line (start -3.2512 -3.8862) (end 3.81 -3.8862) (layer F.SilkS) (width 0.15))
(fp_line (start 3.8608 3.937) (end 3.8608 -3.7846) (layer F.SilkS) (width 0.15))
(fp_line (start -3.8862 3.937) (end 3.7338 3.937) (layer F.SilkS) (width 0.15))
(fp_line (start -5.0292 -2.8448) (end -5.0292 2.794) (layer F.SilkS) (width 0.15))
(fp_line (start -5.0292 2.794) (end -3.8862 2.794) (layer F.SilkS) (width 0.15))
(fp_line (start -3.87604 -3.302) (end -3.29184 -3.8862) (layer F.SilkS) (width 0.15))
(fp_line (start -5.02412 -2.8448) (end -3.87604 -2.8448) (layer F.SilkS) (width 0.15))
(fp_line (start -2.794 -3.8862) (end -2.794 -5.03428) (layer F.SilkS) (width 0.15))
(fp_circle (center -2.83972 -2.86004) (end -2.43332 -2.60604) (layer F.SilkS) (width 0.15))
(pad 8 smd rect (at -4.81584 2.77622) (size 1.99898 0.44958) (layers F.Cu F.Paste F.Mask)
(net 42 /Mikrocontroller/CurrentSense))
(pad 7 smd rect (at -4.81584 1.97612) (size 1.99898 0.44958) (layers F.Cu F.Paste F.Mask)
(net 41 /Mikrocontroller/VOutSense))
(pad 6 smd rect (at -4.81584 1.17602) (size 1.99898 0.44958) (layers F.Cu F.Paste F.Mask)
(net 40 /Mikrocontroller/VInSense))
(pad 5 smd rect (at -4.81584 0.37592) (size 1.99898 0.44958) (layers F.Cu F.Paste F.Mask)
(net 5 +3V3))
(pad 4 smd rect (at -4.81584 -0.42418) (size 1.99898 0.44958) (layers F.Cu F.Paste F.Mask)
(net 19 /Mikrocontroller/RST_N))
(pad 3 smd rect (at -4.81584 -1.22428) (size 1.99898 0.44958) (layers F.Cu F.Paste F.Mask)
(net 7 "Net-(C202-Pad1)"))
(pad 2 smd rect (at -4.81584 -2.02438) (size 1.99898 0.44958) (layers F.Cu F.Paste F.Mask)
(net 6 "Net-(C201-Pad1)"))
(pad 1 smd rect (at -4.81584 -2.82448) (size 1.99898 0.44958) (layers F.Cu F.Paste F.Mask)
(net 5 +3V3))
(pad 24 smd rect (at 4.7498 -2.8194) (size 1.99898 0.44958) (layers F.Cu F.Paste F.Mask)
(net 17 /Mikrocontroller/SWCLK))
(pad 17 smd rect (at 4.7498 2.794) (size 1.99898 0.44958) (layers F.Cu F.Paste F.Mask)
(net 5 +3V3))
(pad 18 smd rect (at 4.7498 1.9812) (size 1.99898 0.44958) (layers F.Cu F.Paste F.Mask)
(net 44 /Mikrocontroller/SW_on))
(pad 19 smd rect (at 4.7498 1.1684) (size 1.99898 0.44958) (layers F.Cu F.Paste F.Mask)
(net 39 /Mikrocontroller/BootstrapPulse))
(pad 20 smd rect (at 4.7498 0.381) (size 1.99898 0.44958) (layers F.Cu F.Paste F.Mask)
(net 24 /Mikrocontroller/DISP_E))
(pad 21 smd rect (at 4.7498 -0.4318) (size 1.99898 0.44958) (layers F.Cu F.Paste F.Mask)
(net 23 /Mikrocontroller/DISP_RW))
(pad 22 smd rect (at 4.7498 -1.2192) (size 1.99898 0.44958) (layers F.Cu F.Paste F.Mask)
(net 22 /Mikrocontroller/DISP_RS))
(pad 23 smd rect (at 4.7498 -2.032) (size 1.99898 0.44958) (layers F.Cu F.Paste F.Mask)
(net 18 /Mikrocontroller/SWDIO))
(pad 32 smd rect (at -2.82448 -4.826) (size 0.44958 1.99898) (layers F.Cu F.Paste F.Mask)
(net 2 GND))
(pad 31 smd rect (at -2.02692 -4.826) (size 0.44958 1.99898) (layers F.Cu F.Paste F.Mask)
(net 38 "Net-(R202-Pad1)"))
(pad 30 smd rect (at -1.22428 -4.826) (size 0.44958 1.99898) (layers F.Cu F.Paste F.Mask)
(net 16 /Mikrocontroller/UART_RX))
(pad 29 smd rect (at -0.42672 -4.826) (size 0.44958 1.99898) (layers F.Cu F.Paste F.Mask)
(net 15 /Mikrocontroller/UART_TX))
(pad 28 smd rect (at 0.37592 -4.826) (size 0.44958 1.99898) (layers F.Cu F.Paste F.Mask)
(net 45 "Net-(U201-Pad28)"))
(pad 27 smd rect (at 1.17348 -4.826) (size 0.44958 1.99898) (layers F.Cu F.Paste F.Mask)
(net 46 "Net-(U201-Pad27)"))
(pad 26 smd rect (at 1.97612 -4.826) (size 0.44958 1.99898) (layers F.Cu F.Paste F.Mask)
(net 47 "Net-(U201-Pad26)"))
(pad 25 smd rect (at 2.77368 -4.826) (size 0.44958 1.99898) (layers F.Cu F.Paste F.Mask)
(net 48 /Mikrocontroller/LOAD_on))
(pad 9 smd rect (at -2.8194 4.7752) (size 0.44958 1.99898) (layers F.Cu F.Paste F.Mask)
(net 49 "Net-(U201-Pad9)"))
(pad 10 smd rect (at -2.032 4.7752) (size 0.44958 1.99898) (layers F.Cu F.Paste F.Mask)
(net 29 /Mikrocontroller/DISP_D0))
(pad 11 smd rect (at -1.2192 4.7752) (size 0.44958 1.99898) (layers F.Cu F.Paste F.Mask)
(net 30 /Mikrocontroller/DISP_D1))
(pad 12 smd rect (at -0.4318 4.7752) (size 0.44958 1.99898) (layers F.Cu F.Paste F.Mask)
(net 31 /Mikrocontroller/DISP_D2))
(pad 13 smd rect (at 0.3556 4.7752) (size 0.44958 1.99898) (layers F.Cu F.Paste F.Mask)
(net 32 /Mikrocontroller/DISP_D3))
(pad 14 smd rect (at 1.1684 4.7752) (size 0.44958 1.99898) (layers F.Cu F.Paste F.Mask)
(net 50 "Net-(U201-Pad14)"))
(pad 15 smd rect (at 1.9812 4.7752) (size 0.44958 1.99898) (layers F.Cu F.Paste F.Mask)
(net 51 "Net-(U201-Pad15)"))
(pad 16 smd rect (at 2.794 4.7752) (size 0.44958 1.99898) (layers F.Cu F.Paste F.Mask)
(net 2 GND))
(model SMD_Packages/TQFP-32.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module SMD_Packages:SOIC-8-W (layer B.Cu) (tedit 577433D3) (tstamp 576C3F5F)
(at 61.365 20.833 180)
(descr "module SMD SOIC SOJ 8 pins etroit")
(tags "CMS SOJ")
(path /575B1260/575B3D7F)
(attr smd)
(fp_text reference U301 (at 0 0.889 180) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value MIC4604YM (at 0 -1.016 180) (layer B.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -2.667 -1.778) (end -2.667 -1.905) (layer B.SilkS) (width 0.15))
(fp_line (start -2.667 -1.905) (end 2.667 -1.905) (layer B.SilkS) (width 0.15))
(fp_line (start 2.667 1.905) (end -2.667 1.905) (layer B.SilkS) (width 0.15))
(fp_line (start -2.667 1.905) (end -2.667 -1.778) (layer B.SilkS) (width 0.15))
(fp_line (start -2.667 0.508) (end -2.159 0.508) (layer B.SilkS) (width 0.15))
(fp_line (start -2.159 0.508) (end -2.159 -0.508) (layer B.SilkS) (width 0.15))
(fp_line (start -2.159 -0.508) (end -2.667 -0.508) (layer B.SilkS) (width 0.15))
(fp_line (start 2.667 1.905) (end 2.667 -1.905) (layer B.SilkS) (width 0.15))
(pad 8 smd rect (at -1.905 2.667 180) (size 0.59944 1.39954) (layers B.Cu B.Paste B.Mask)
(net 37 "/Power Converter/LoadDrive"))
(pad 1 smd rect (at -1.905 -2.667 180) (size 0.59944 1.39954) (layers B.Cu B.Paste B.Mask)
(net 3 +12V))
(pad 7 smd rect (at -0.635 2.667 180) (size 0.59944 1.39954) (layers B.Cu B.Paste B.Mask)
(net 2 GND))
(pad 6 smd rect (at 0.635 2.667 180) (size 0.59944 1.39954) (layers B.Cu B.Paste B.Mask)
(net 52 "Net-(R309-Pad1)"))
(pad 5 smd rect (at 1.905 2.667 180) (size 0.59944 1.39954) (layers B.Cu B.Paste B.Mask)
(net 53 "Net-(R310-Pad1)"))
(pad 2 smd rect (at -0.635 -2.667 180) (size 0.59944 1.39954) (layers B.Cu B.Paste B.Mask)
(net 8 "Net-(C302-Pad1)"))
(pad 3 smd rect (at 0.635 -2.667 180) (size 0.59944 1.39954) (layers B.Cu B.Paste B.Mask)
(net 54 "Net-(R311-Pad2)"))
(pad 4 smd rect (at 1.905 -2.667 180) (size 0.59944 1.39954) (layers B.Cu B.Paste B.Mask)
(net 9 "Net-(C302-Pad2)"))
(model SMD_Packages/SOIC-8-W.wrl
(at (xyz 0 0 0))
(scale (xyz 0.5 0.32 0.5))
(rotate (xyz 0 0 0))
)
)
(module SMD_Packages:SOT-23-5 (layer B.Cu) (tedit 577433E6) (tstamp 576C3F68)
(at 31.805 41.0075 270)
(path /575B1260/575B4C3B)
(attr smd)
(fp_text reference U302 (at 0.0135 2.341 270) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value MCP6001 (at -0.8755 -6.93 270) (layer B.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start 1.524 0.889) (end 1.524 -0.889) (layer B.SilkS) (width 0.15))
(fp_line (start 1.524 -0.889) (end -1.524 -0.889) (layer B.SilkS) (width 0.15))
(fp_line (start -1.524 -0.889) (end -1.524 0.889) (layer B.SilkS) (width 0.15))
(fp_line (start -1.524 0.889) (end 1.524 0.889) (layer B.SilkS) (width 0.15))
(pad 1 smd rect (at -0.9525 -1.27 270) (size 0.508 0.762) (layers B.Cu B.Paste B.Mask)
(net 42 /Mikrocontroller/CurrentSense))
(pad 3 smd rect (at 0.9525 -1.27 270) (size 0.508 0.762) (layers B.Cu B.Paste B.Mask)
(net 11 "/Power Converter/Bat-"))
(pad 5 smd rect (at -0.9525 1.27 270) (size 0.508 0.762) (layers B.Cu B.Paste B.Mask)
(net 5 +3V3))
(pad 2 smd rect (at 0 -1.27 270) (size 0.508 0.762) (layers B.Cu B.Paste B.Mask)
(net 2 GND))
(pad 4 smd rect (at 0.9525 1.27 270) (size 0.508 0.762) (layers B.Cu B.Paste B.Mask)
(net 43 "Net-(R307-Pad2)"))
(model SMD_Packages/SOT-23-5.wrl
(at (xyz 0 0 0))
(scale (xyz 0.1 0.1 0.1))
(rotate (xyz 0 0 0))
)
)
(module Crystals:Crystal_HC49-U_Vertical (layer F.Cu) (tedit 0) (tstamp 576C3F6E)
(at 46 50.17094 270)
(descr "Crystal, Quarz, HC49/U, vertical, stehend,")
(tags "Crystal, Quarz, HC49/U, vertical, stehend,")
(path /5761A543/5761C583)
(fp_text reference Y201 (at -0.13294 0.026 270) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 8MHz (at 0 3.81 270) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 4.699 -1.00076) (end 4.89966 -0.59944) (layer F.SilkS) (width 0.15))
(fp_line (start 4.89966 -0.59944) (end 5.00126 0) (layer F.SilkS) (width 0.15))
(fp_line (start 5.00126 0) (end 4.89966 0.50038) (layer F.SilkS) (width 0.15))
(fp_line (start 4.89966 0.50038) (end 4.50088 1.19888) (layer F.SilkS) (width 0.15))
(fp_line (start 4.50088 1.19888) (end 3.8989 1.6002) (layer F.SilkS) (width 0.15))
(fp_line (start 3.8989 1.6002) (end 3.29946 1.80086) (layer F.SilkS) (width 0.15))
(fp_line (start 3.29946 1.80086) (end -3.29946 1.80086) (layer F.SilkS) (width 0.15))
(fp_line (start -3.29946 1.80086) (end -4.0005 1.6002) (layer F.SilkS) (width 0.15))
(fp_line (start -4.0005 1.6002) (end -4.39928 1.30048) (layer F.SilkS) (width 0.15))
(fp_line (start -4.39928 1.30048) (end -4.8006 0.8001) (layer F.SilkS) (width 0.15))
(fp_line (start -4.8006 0.8001) (end -5.00126 0.20066) (layer F.SilkS) (width 0.15))
(fp_line (start -5.00126 0.20066) (end -5.00126 -0.29972) (layer F.SilkS) (width 0.15))
(fp_line (start -5.00126 -0.29972) (end -4.8006 -0.8001) (layer F.SilkS) (width 0.15))
(fp_line (start -4.8006 -0.8001) (end -4.30022 -1.39954) (layer F.SilkS) (width 0.15))
(fp_line (start -4.30022 -1.39954) (end -3.79984 -1.69926) (layer F.SilkS) (width 0.15))
(fp_line (start -3.79984 -1.69926) (end -3.29946 -1.80086) (layer F.SilkS) (width 0.15))
(fp_line (start -3.2004 -1.80086) (end 3.40106 -1.80086) (layer F.SilkS) (width 0.15))
(fp_line (start 3.40106 -1.80086) (end 3.79984 -1.69926) (layer F.SilkS) (width 0.15))
(fp_line (start 3.79984 -1.69926) (end 4.30022 -1.39954) (layer F.SilkS) (width 0.15))
(fp_line (start 4.30022 -1.39954) (end 4.8006 -0.89916) (layer F.SilkS) (width 0.15))
(fp_line (start -3.19024 -2.32918) (end -3.64998 -2.28092) (layer F.SilkS) (width 0.15))
(fp_line (start -3.64998 -2.28092) (end -4.04876 -2.16916) (layer F.SilkS) (width 0.15))
(fp_line (start -4.04876 -2.16916) (end -4.48056 -1.95072) (layer F.SilkS) (width 0.15))
(fp_line (start -4.48056 -1.95072) (end -4.77012 -1.71958) (layer F.SilkS) (width 0.15))
(fp_line (start -4.77012 -1.71958) (end -5.10032 -1.36906) (layer F.SilkS) (width 0.15))
(fp_line (start -5.10032 -1.36906) (end -5.38988 -0.83058) (layer F.SilkS) (width 0.15))
(fp_line (start -5.38988 -0.83058) (end -5.51942 -0.23114) (layer F.SilkS) (width 0.15))
(fp_line (start -5.51942 -0.23114) (end -5.51942 0.2794) (layer F.SilkS) (width 0.15))
(fp_line (start -5.51942 0.2794) (end -5.34924 0.98044) (layer F.SilkS) (width 0.15))
(fp_line (start -5.34924 0.98044) (end -4.95046 1.56972) (layer F.SilkS) (width 0.15))
(fp_line (start -4.95046 1.56972) (end -4.49072 1.94056) (layer F.SilkS) (width 0.15))
(fp_line (start -4.49072 1.94056) (end -4.06908 2.14884) (layer F.SilkS) (width 0.15))
(fp_line (start -4.06908 2.14884) (end -3.6195 2.30886) (layer F.SilkS) (width 0.15))
(fp_line (start -3.6195 2.30886) (end -3.18008 2.33934) (layer F.SilkS) (width 0.15))
(fp_line (start 4.16052 2.1209) (end 4.53898 1.89992) (layer F.SilkS) (width 0.15))
(fp_line (start 4.53898 1.89992) (end 4.85902 1.62052) (layer F.SilkS) (width 0.15))
(fp_line (start 4.85902 1.62052) (end 5.11048 1.29032) (layer F.SilkS) (width 0.15))
(fp_line (start 5.11048 1.29032) (end 5.4102 0.73914) (layer F.SilkS) (width 0.15))
(fp_line (start 5.4102 0.73914) (end 5.51942 0.26924) (layer F.SilkS) (width 0.15))
(fp_line (start 5.51942 0.26924) (end 5.53974 -0.1905) (layer F.SilkS) (width 0.15))
(fp_line (start 5.53974 -0.1905) (end 5.45084 -0.65024) (layer F.SilkS) (width 0.15))
(fp_line (start 5.45084 -0.65024) (end 5.26034 -1.09982) (layer F.SilkS) (width 0.15))
(fp_line (start 5.26034 -1.09982) (end 4.89966 -1.56972) (layer F.SilkS) (width 0.15))
(fp_line (start 4.89966 -1.56972) (end 4.54914 -1.88976) (layer F.SilkS) (width 0.15))
(fp_line (start 4.54914 -1.88976) (end 4.16052 -2.1209) (layer F.SilkS) (width 0.15))
(fp_line (start 4.16052 -2.1209) (end 3.73126 -2.2606) (layer F.SilkS) (width 0.15))
(fp_line (start 3.73126 -2.2606) (end 3.2893 -2.32918) (layer F.SilkS) (width 0.15))
(fp_line (start -3.2004 2.32918) (end 3.2512 2.32918) (layer F.SilkS) (width 0.15))
(fp_line (start 3.2512 2.32918) (end 3.6703 2.29108) (layer F.SilkS) (width 0.15))
(fp_line (start 3.6703 2.29108) (end 4.16052 2.1209) (layer F.SilkS) (width 0.15))
(fp_line (start -3.2004 -2.32918) (end 3.2512 -2.32918) (layer F.SilkS) (width 0.15))
(pad 1 thru_hole circle (at -2.44094 0 270) (size 1.50114 1.50114) (drill 0.8001) (layers *.Cu *.Mask F.SilkS)
(net 6 "Net-(C201-Pad1)"))
(pad 2 thru_hole circle (at 2.44094 0 270) (size 1.50114 1.50114) (drill 0.8001) (layers *.Cu *.Mask F.SilkS)
(net 7 "Net-(C202-Pad1)"))
)
(module Capacitors_ThroughHole:C_Radial_D5_L11_P2.5 (layer F.Cu) (tedit 0) (tstamp 576ED8D9)
(at 57.19 60.325)
(descr "Radial Electrolytic Capacitor Diameter 5mm x Length 11mm, Pitch 2.5mm")
(tags "Electrolytic Capacitor")
(path /575C88A3)
(fp_text reference C102 (at 5.929 1.016) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 100u (at 1.25 3.8) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.325 -2.499) (end 1.325 2.499) (layer F.SilkS) (width 0.15))
(fp_line (start 1.465 -2.491) (end 1.465 2.491) (layer F.SilkS) (width 0.15))
(fp_line (start 1.605 -2.475) (end 1.605 -0.095) (layer F.SilkS) (width 0.15))
(fp_line (start 1.605 0.095) (end 1.605 2.475) (layer F.SilkS) (width 0.15))
(fp_line (start 1.745 -2.451) (end 1.745 -0.49) (layer F.SilkS) (width 0.15))
(fp_line (start 1.745 0.49) (end 1.745 2.451) (layer F.SilkS) (width 0.15))
(fp_line (start 1.885 -2.418) (end 1.885 -0.657) (layer F.SilkS) (width 0.15))
(fp_line (start 1.885 0.657) (end 1.885 2.418) (layer F.SilkS) (width 0.15))
(fp_line (start 2.025 -2.377) (end 2.025 -0.764) (layer F.SilkS) (width 0.15))
(fp_line (start 2.025 0.764) (end 2.025 2.377) (layer F.SilkS) (width 0.15))
(fp_line (start 2.165 -2.327) (end 2.165 -0.835) (layer F.SilkS) (width 0.15))
(fp_line (start 2.165 0.835) (end 2.165 2.327) (layer F.SilkS) (width 0.15))
(fp_line (start 2.305 -2.266) (end 2.305 -0.879) (layer F.SilkS) (width 0.15))
(fp_line (start 2.305 0.879) (end 2.305 2.266) (layer F.SilkS) (width 0.15))
(fp_line (start 2.445 -2.196) (end 2.445 -0.898) (layer F.SilkS) (width 0.15))
(fp_line (start 2.445 0.898) (end 2.445 2.196) (layer F.SilkS) (width 0.15))
(fp_line (start 2.585 -2.114) (end 2.585 -0.896) (layer F.SilkS) (width 0.15))
(fp_line (start 2.585 0.896) (end 2.585 2.114) (layer F.SilkS) (width 0.15))
(fp_line (start 2.725 -2.019) (end 2.725 -0.871) (layer F.SilkS) (width 0.15))
(fp_line (start 2.725 0.871) (end 2.725 2.019) (layer F.SilkS) (width 0.15))
(fp_line (start 2.865 -1.908) (end 2.865 -0.823) (layer F.SilkS) (width 0.15))
(fp_line (start 2.865 0.823) (end 2.865 1.908) (layer F.SilkS) (width 0.15))
(fp_line (start 3.005 -1.78) (end 3.005 -0.745) (layer F.SilkS) (width 0.15))
(fp_line (start 3.005 0.745) (end 3.005 1.78) (layer F.SilkS) (width 0.15))
(fp_line (start 3.145 -1.631) (end 3.145 -0.628) (layer F.SilkS) (width 0.15))
(fp_line (start 3.145 0.628) (end 3.145 1.631) (layer F.SilkS) (width 0.15))
(fp_line (start 3.285 -1.452) (end 3.285 -0.44) (layer F.SilkS) (width 0.15))
(fp_line (start 3.285 0.44) (end 3.285 1.452) (layer F.SilkS) (width 0.15))
(fp_line (start 3.425 -1.233) (end 3.425 1.233) (layer F.SilkS) (width 0.15))
(fp_line (start 3.565 -0.944) (end 3.565 0.944) (layer F.SilkS) (width 0.15))
(fp_line (start 3.705 -0.472) (end 3.705 0.472) (layer F.SilkS) (width 0.15))
(fp_circle (center 2.5 0) (end 2.5 -0.9) (layer F.SilkS) (width 0.15))
(fp_circle (center 1.25 0) (end 1.25 -2.5375) (layer F.SilkS) (width 0.15))
(fp_circle (center 1.25 0) (end 1.25 -2.8) (layer F.CrtYd) (width 0.05))
(pad 1 thru_hole rect (at 0 0) (size 1.3 1.3) (drill 0.8) (layers *.Cu *.Mask F.SilkS)
(net 3 +12V))
(pad 2 thru_hole circle (at 2.5 0) (size 1.3 1.3) (drill 0.8) (layers *.Cu *.Mask F.SilkS)
(net 2 GND))
(model Capacitors_ThroughHole.3dshapes/C_Radial_D5_L11_P2.5.wrl
(at (xyz 0.049213 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 90))
)
)
(module Capacitors_ThroughHole:C_Radial_D5_L11_P2.5 (layer F.Cu) (tedit 0) (tstamp 576ED8DE)
(at 49.53 64.897 270)
(descr "Radial Electrolytic Capacitor Diameter 5mm x Length 11mm, Pitch 2.5mm")
(tags "Electrolytic Capacitor")
(path /5761FB5A)
(fp_text reference C104 (at 1.27 3.175 270) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 100u (at 1.25 3.8 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.325 -2.499) (end 1.325 2.499) (layer F.SilkS) (width 0.15))
(fp_line (start 1.465 -2.491) (end 1.465 2.491) (layer F.SilkS) (width 0.15))
(fp_line (start 1.605 -2.475) (end 1.605 -0.095) (layer F.SilkS) (width 0.15))
(fp_line (start 1.605 0.095) (end 1.605 2.475) (layer F.SilkS) (width 0.15))
(fp_line (start 1.745 -2.451) (end 1.745 -0.49) (layer F.SilkS) (width 0.15))
(fp_line (start 1.745 0.49) (end 1.745 2.451) (layer F.SilkS) (width 0.15))
(fp_line (start 1.885 -2.418) (end 1.885 -0.657) (layer F.SilkS) (width 0.15))
(fp_line (start 1.885 0.657) (end 1.885 2.418) (layer F.SilkS) (width 0.15))
(fp_line (start 2.025 -2.377) (end 2.025 -0.764) (layer F.SilkS) (width 0.15))
(fp_line (start 2.025 0.764) (end 2.025 2.377) (layer F.SilkS) (width 0.15))
(fp_line (start 2.165 -2.327) (end 2.165 -0.835) (layer F.SilkS) (width 0.15))
(fp_line (start 2.165 0.835) (end 2.165 2.327) (layer F.SilkS) (width 0.15))
(fp_line (start 2.305 -2.266) (end 2.305 -0.879) (layer F.SilkS) (width 0.15))
(fp_line (start 2.305 0.879) (end 2.305 2.266) (layer F.SilkS) (width 0.15))
(fp_line (start 2.445 -2.196) (end 2.445 -0.898) (layer F.SilkS) (width 0.15))
(fp_line (start 2.445 0.898) (end 2.445 2.196) (layer F.SilkS) (width 0.15))
(fp_line (start 2.585 -2.114) (end 2.585 -0.896) (layer F.SilkS) (width 0.15))
(fp_line (start 2.585 0.896) (end 2.585 2.114) (layer F.SilkS) (width 0.15))
(fp_line (start 2.725 -2.019) (end 2.725 -0.871) (layer F.SilkS) (width 0.15))
(fp_line (start 2.725 0.871) (end 2.725 2.019) (layer F.SilkS) (width 0.15))
(fp_line (start 2.865 -1.908) (end 2.865 -0.823) (layer F.SilkS) (width 0.15))
(fp_line (start 2.865 0.823) (end 2.865 1.908) (layer F.SilkS) (width 0.15))
(fp_line (start 3.005 -1.78) (end 3.005 -0.745) (layer F.SilkS) (width 0.15))
(fp_line (start 3.005 0.745) (end 3.005 1.78) (layer F.SilkS) (width 0.15))
(fp_line (start 3.145 -1.631) (end 3.145 -0.628) (layer F.SilkS) (width 0.15))
(fp_line (start 3.145 0.628) (end 3.145 1.631) (layer F.SilkS) (width 0.15))
(fp_line (start 3.285 -1.452) (end 3.285 -0.44) (layer F.SilkS) (width 0.15))
(fp_line (start 3.285 0.44) (end 3.285 1.452) (layer F.SilkS) (width 0.15))
(fp_line (start 3.425 -1.233) (end 3.425 1.233) (layer F.SilkS) (width 0.15))
(fp_line (start 3.565 -0.944) (end 3.565 0.944) (layer F.SilkS) (width 0.15))
(fp_line (start 3.705 -0.472) (end 3.705 0.472) (layer F.SilkS) (width 0.15))
(fp_circle (center 2.5 0) (end 2.5 -0.9) (layer F.SilkS) (width 0.15))
(fp_circle (center 1.25 0) (end 1.25 -2.5375) (layer F.SilkS) (width 0.15))
(fp_circle (center 1.25 0) (end 1.25 -2.8) (layer F.CrtYd) (width 0.05))
(pad 1 thru_hole rect (at 0 0 270) (size 1.3 1.3) (drill 0.8) (layers *.Cu *.Mask F.SilkS)
(net 4 +5V))
(pad 2 thru_hole circle (at 2.5 0 270) (size 1.3 1.3) (drill 0.8) (layers *.Cu *.Mask F.SilkS)
(net 2 GND))
(model Capacitors_ThroughHole.3dshapes/C_Radial_D5_L11_P2.5.wrl
(at (xyz 0.049213 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 90))
)
)
(module Capacitors_ThroughHole:C_Radial_D5_L11_P2.5 (layer F.Cu) (tedit 0) (tstamp 576ED8E3)
(at 56.769 64.897 270)
(descr "Radial Electrolytic Capacitor Diameter 5mm x Length 11mm, Pitch 2.5mm")
(tags "Electrolytic Capacitor")
(path /576205C7)
(fp_text reference C105 (at 1.27 3.302 270) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 100u (at 1.25 3.8 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.325 -2.499) (end 1.325 2.499) (layer F.SilkS) (width 0.15))
(fp_line (start 1.465 -2.491) (end 1.465 2.491) (layer F.SilkS) (width 0.15))
(fp_line (start 1.605 -2.475) (end 1.605 -0.095) (layer F.SilkS) (width 0.15))
(fp_line (start 1.605 0.095) (end 1.605 2.475) (layer F.SilkS) (width 0.15))
(fp_line (start 1.745 -2.451) (end 1.745 -0.49) (layer F.SilkS) (width 0.15))
(fp_line (start 1.745 0.49) (end 1.745 2.451) (layer F.SilkS) (width 0.15))
(fp_line (start 1.885 -2.418) (end 1.885 -0.657) (layer F.SilkS) (width 0.15))
(fp_line (start 1.885 0.657) (end 1.885 2.418) (layer F.SilkS) (width 0.15))
(fp_line (start 2.025 -2.377) (end 2.025 -0.764) (layer F.SilkS) (width 0.15))
(fp_line (start 2.025 0.764) (end 2.025 2.377) (layer F.SilkS) (width 0.15))
(fp_line (start 2.165 -2.327) (end 2.165 -0.835) (layer F.SilkS) (width 0.15))
(fp_line (start 2.165 0.835) (end 2.165 2.327) (layer F.SilkS) (width 0.15))
(fp_line (start 2.305 -2.266) (end 2.305 -0.879) (layer F.SilkS) (width 0.15))
(fp_line (start 2.305 0.879) (end 2.305 2.266) (layer F.SilkS) (width 0.15))
(fp_line (start 2.445 -2.196) (end 2.445 -0.898) (layer F.SilkS) (width 0.15))
(fp_line (start 2.445 0.898) (end 2.445 2.196) (layer F.SilkS) (width 0.15))
(fp_line (start 2.585 -2.114) (end 2.585 -0.896) (layer F.SilkS) (width 0.15))
(fp_line (start 2.585 0.896) (end 2.585 2.114) (layer F.SilkS) (width 0.15))
(fp_line (start 2.725 -2.019) (end 2.725 -0.871) (layer F.SilkS) (width 0.15))
(fp_line (start 2.725 0.871) (end 2.725 2.019) (layer F.SilkS) (width 0.15))
(fp_line (start 2.865 -1.908) (end 2.865 -0.823) (layer F.SilkS) (width 0.15))
(fp_line (start 2.865 0.823) (end 2.865 1.908) (layer F.SilkS) (width 0.15))
(fp_line (start 3.005 -1.78) (end 3.005 -0.745) (layer F.SilkS) (width 0.15))
(fp_line (start 3.005 0.745) (end 3.005 1.78) (layer F.SilkS) (width 0.15))
(fp_line (start 3.145 -1.631) (end 3.145 -0.628) (layer F.SilkS) (width 0.15))
(fp_line (start 3.145 0.628) (end 3.145 1.631) (layer F.SilkS) (width 0.15))
(fp_line (start 3.285 -1.452) (end 3.285 -0.44) (layer F.SilkS) (width 0.15))
(fp_line (start 3.285 0.44) (end 3.285 1.452) (layer F.SilkS) (width 0.15))
(fp_line (start 3.425 -1.233) (end 3.425 1.233) (layer F.SilkS) (width 0.15))
(fp_line (start 3.565 -0.944) (end 3.565 0.944) (layer F.SilkS) (width 0.15))
(fp_line (start 3.705 -0.472) (end 3.705 0.472) (layer F.SilkS) (width 0.15))
(fp_circle (center 2.5 0) (end 2.5 -0.9) (layer F.SilkS) (width 0.15))
(fp_circle (center 1.25 0) (end 1.25 -2.5375) (layer F.SilkS) (width 0.15))
(fp_circle (center 1.25 0) (end 1.25 -2.8) (layer F.CrtYd) (width 0.05))
(pad 1 thru_hole rect (at 0 0 270) (size 1.3 1.3) (drill 0.8) (layers *.Cu *.Mask F.SilkS)
(net 5 +3V3))
(pad 2 thru_hole circle (at 2.5 0 270) (size 1.3 1.3) (drill 0.8) (layers *.Cu *.Mask F.SilkS)
(net 2 GND))
(model Capacitors_ThroughHole.3dshapes/C_Radial_D5_L11_P2.5.wrl
(at (xyz 0.049213 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 90))
)
)
(module Capacitors_ThroughHole:C_Radial_D10_L13_P5 (layer F.Cu) (tedit 0) (tstamp 576ED8E8)
(at 38.807415 22.072097 180)
(descr "Radial Electrolytic Capacitor Diameter 10mm x Length 13mm, Pitch 5mm")
(tags "Electrolytic Capacitor")
(path /575B1260/575B17F1)
(fp_text reference C303 (at 2.5 -6.3 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 100uF (at 2.5 6.3 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 2.575 -4.999) (end 2.575 4.999) (layer F.SilkS) (width 0.15))
(fp_line (start 2.715 -4.995) (end 2.715 4.995) (layer F.SilkS) (width 0.15))
(fp_line (start 2.855 -4.987) (end 2.855 4.987) (layer F.SilkS) (width 0.15))
(fp_line (start 2.995 -4.975) (end 2.995 4.975) (layer F.SilkS) (width 0.15))
(fp_line (start 3.135 -4.96) (end 3.135 4.96) (layer F.SilkS) (width 0.15))
(fp_line (start 3.275 -4.94) (end 3.275 4.94) (layer F.SilkS) (width 0.15))
(fp_line (start 3.415 -4.916) (end 3.415 4.916) (layer F.SilkS) (width 0.15))
(fp_line (start 3.555 -4.887) (end 3.555 4.887) (layer F.SilkS) (width 0.15))
(fp_line (start 3.695 -4.855) (end 3.695 4.855) (layer F.SilkS) (width 0.15))
(fp_line (start 3.835 -4.818) (end 3.835 4.818) (layer F.SilkS) (width 0.15))
(fp_line (start 3.975 -4.777) (end 3.975 4.777) (layer F.SilkS) (width 0.15))
(fp_line (start 4.115 -4.732) (end 4.115 -0.466) (layer F.SilkS) (width 0.15))
(fp_line (start 4.115 0.466) (end 4.115 4.732) (layer F.SilkS) (width 0.15))
(fp_line (start 4.255 -4.682) (end 4.255 -0.667) (layer F.SilkS) (width 0.15))
(fp_line (start 4.255 0.667) (end 4.255 4.682) (layer F.SilkS) (width 0.15))
(fp_line (start 4.395 -4.627) (end 4.395 -0.796) (layer F.SilkS) (width 0.15))
(fp_line (start 4.395 0.796) (end 4.395 4.627) (layer F.SilkS) (width 0.15))
(fp_line (start 4.535 -4.567) (end 4.535 -0.885) (layer F.SilkS) (width 0.15))
(fp_line (start 4.535 0.885) (end 4.535 4.567) (layer F.SilkS) (width 0.15))
(fp_line (start 4.675 -4.502) (end 4.675 -0.946) (layer F.SilkS) (width 0.15))
(fp_line (start 4.675 0.946) (end 4.675 4.502) (layer F.SilkS) (width 0.15))
(fp_line (start 4.815 -4.432) (end 4.815 -0.983) (layer F.SilkS) (width 0.15))
(fp_line (start 4.815 0.983) (end 4.815 4.432) (layer F.SilkS) (width 0.15))
(fp_line (start 4.955 -4.356) (end 4.955 -0.999) (layer F.SilkS) (width 0.15))
(fp_line (start 4.955 0.999) (end 4.955 4.356) (layer F.SilkS) (width 0.15))
(fp_line (start 5.095 -4.274) (end 5.095 -0.995) (layer F.SilkS) (width 0.15))
(fp_line (start 5.095 0.995) (end 5.095 4.274) (layer F.SilkS) (width 0.15))
(fp_line (start 5.235 -4.186) (end 5.235 -0.972) (layer F.SilkS) (width 0.15))
(fp_line (start 5.235 0.972) (end 5.235 4.186) (layer F.SilkS) (width 0.15))
(fp_line (start 5.375 -4.091) (end 5.375 -0.927) (layer F.SilkS) (width 0.15))
(fp_line (start 5.375 0.927) (end 5.375 4.091) (layer F.SilkS) (width 0.15))
(fp_line (start 5.515 -3.989) (end 5.515 -0.857) (layer F.SilkS) (width 0.15))
(fp_line (start 5.515 0.857) (end 5.515 3.989) (layer F.SilkS) (width 0.15))
(fp_line (start 5.655 -3.879) (end 5.655 -0.756) (layer F.SilkS) (width 0.15))
(fp_line (start 5.655 0.756) (end 5.655 3.879) (layer F.SilkS) (width 0.15))
(fp_line (start 5.795 -3.761) (end 5.795 -0.607) (layer F.SilkS) (width 0.15))
(fp_line (start 5.795 0.607) (end 5.795 3.761) (layer F.SilkS) (width 0.15))
(fp_line (start 5.935 -3.633) (end 5.935 -0.355) (layer F.SilkS) (width 0.15))
(fp_line (start 5.935 0.355) (end 5.935 3.633) (layer F.SilkS) (width 0.15))
(fp_line (start 6.075 -3.496) (end 6.075 3.496) (layer F.SilkS) (width 0.15))
(fp_line (start 6.215 -3.346) (end 6.215 3.346) (layer F.SilkS) (width 0.15))
(fp_line (start 6.355 -3.184) (end 6.355 3.184) (layer F.SilkS) (width 0.15))
(fp_line (start 6.495 -3.007) (end 6.495 3.007) (layer F.SilkS) (width 0.15))
(fp_line (start 6.635 -2.811) (end 6.635 2.811) (layer F.SilkS) (width 0.15))
(fp_line (start 6.775 -2.593) (end 6.775 2.593) (layer F.SilkS) (width 0.15))
(fp_line (start 6.915 -2.347) (end 6.915 2.347) (layer F.SilkS) (width 0.15))
(fp_line (start 7.055 -2.062) (end 7.055 2.062) (layer F.SilkS) (width 0.15))
(fp_line (start 7.195 -1.72) (end 7.195 1.72) (layer F.SilkS) (width 0.15))
(fp_line (start 7.335 -1.274) (end 7.335 1.274) (layer F.SilkS) (width 0.15))
(fp_line (start 7.475 -0.499) (end 7.475 0.499) (layer F.SilkS) (width 0.15))
(fp_circle (center 5 0) (end 5 -1) (layer F.SilkS) (width 0.15))
(fp_circle (center 2.5 0) (end 2.5 -5.0375) (layer F.SilkS) (width 0.15))
(fp_circle (center 2.5 0) (end 2.5 -5.3) (layer F.CrtYd) (width 0.05))
(pad 1 thru_hole rect (at 0 0 180) (size 1.3 1.3) (drill 0.8) (layers *.Cu *.Mask F.SilkS)
(net 10 "/Power Converter/VInDirect"))
(pad 2 thru_hole circle (at 5 0 180) (size 1.3 1.3) (drill 0.8) (layers *.Cu *.Mask F.SilkS)
(net 2 GND))
(model Capacitors_ThroughHole.3dshapes/C_Radial_D10_L13_P5.wrl
(at (xyz 0.0984252 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 90))
)
)
(module Discret:R3-LARGE_PADS (layer F.Cu) (tedit 576EE222) (tstamp 576EE248)
(at 29 21.19 90)
(descr "Resitance 3 pas")
(tags R)
(path /575B1260/576B0104)
(fp_text reference D301 (at 0 0 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value D (at 0 0 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -3.81 0) (end -3.302 0) (layer F.SilkS) (width 0.15))
(fp_line (start 3.81 0) (end 3.302 0) (layer F.SilkS) (width 0.15))
(fp_line (start 3.302 0) (end 3.302 -1.016) (layer F.SilkS) (width 0.15))
(fp_line (start 3.302 -1.016) (end -3.302 -1.016) (layer F.SilkS) (width 0.15))
(fp_line (start -3.302 -1.016) (end -3.302 1.016) (layer F.SilkS) (width 0.15))
(fp_line (start -3.302 1.016) (end 3.302 1.016) (layer F.SilkS) (width 0.15))
(fp_line (start 3.302 1.016) (end 3.302 0) (layer F.SilkS) (width 0.15))
(fp_line (start -3.302 -0.508) (end -2.794 -1.016) (layer F.SilkS) (width 0.15))
(pad 1 thru_hole circle (at -3.81 0 90) (size 2 2) (drill 1.2) (layers *.Cu *.Mask F.SilkS)
(net 12 "Net-(D301-Pad1)"))
(pad 2 thru_hole circle (at 3.81 0 90) (size 2 2) (drill 1.2) (layers *.Cu *.Mask F.SilkS)
(net 13 "/Power Converter/Vpanel"))
(model Discret.3dshapes/R3-LARGE_PADS.wrl
(at (xyz 0 0 0))
(scale (xyz 0.3 0.3 0.3))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0805_HandSoldering (layer B.Cu) (tedit 577433E0) (tstamp 577430A5)
(at 27.813 41.148 270)
(descr "Capacitor SMD 0805, hand soldering")
(tags "capacitor 0805")
(path /575B1260/57743353)
(attr smd)
(fp_text reference C305 (at 0 2.1 270) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 1uF (at 0 -2.1 270) (layer B.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -2.3 1) (end 2.3 1) (layer B.CrtYd) (width 0.05))
(fp_line (start -2.3 -1) (end 2.3 -1) (layer B.CrtYd) (width 0.05))
(fp_line (start -2.3 1) (end -2.3 -1) (layer B.CrtYd) (width 0.05))
(fp_line (start 2.3 1) (end 2.3 -1) (layer B.CrtYd) (width 0.05))
(fp_line (start 0.5 0.85) (end -0.5 0.85) (layer B.SilkS) (width 0.15))
(fp_line (start -0.5 -0.85) (end 0.5 -0.85) (layer B.SilkS) (width 0.15))
(pad 1 smd rect (at -1.25 0 270) (size 1.5 1.25) (layers B.Cu B.Paste B.Mask)
(net 5 +3V3))
(pad 2 smd rect (at 1.25 0 270) (size 1.5 1.25) (layers B.Cu B.Paste B.Mask)
(net 2 GND))
(model Capacitors_SMD/C_0805_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0805_HandSoldering (layer B.Cu) (tedit 57D1BC9D) (tstamp 57CF37E8)
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(at 65.913 26.269 270)
(descr "Capacitor SMD 0805, hand soldering")
(tags "capacitor 0805")
(path /575B1260/575B423F)
(attr smd)
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(fp_text reference C301 (at -4.044 1.016 270) (layer B.SilkS)
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(fp_text value 22uF (at 0 -2.1 270) (layer B.SilkS) hide
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -2.3 1) (end 2.3 1) (layer B.CrtYd) (width 0.05))
(fp_line (start -2.3 -1) (end 2.3 -1) (layer B.CrtYd) (width 0.05))
(fp_line (start -2.3 1) (end -2.3 -1) (layer B.CrtYd) (width 0.05))
(fp_line (start 2.3 1) (end 2.3 -1) (layer B.CrtYd) (width 0.05))
(fp_line (start 0.5 0.85) (end -0.5 0.85) (layer B.SilkS) (width 0.15))
(fp_line (start -0.5 -0.85) (end 0.5 -0.85) (layer B.SilkS) (width 0.15))
(pad 1 smd rect (at -1.25 0 270) (size 1.5 1.25) (layers B.Cu B.Paste B.Mask)
(net 3 +12V))
(pad 2 smd rect (at 1.25 0 270) (size 1.5 1.25) (layers B.Cu B.Paste B.Mask)
(net 2 GND))
(model Capacitors_SMD/C_0805_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(module Capacitors_SMD:C_0603_HandSoldering (layer B.Cu) (tedit 57D1BC61) (tstamp 57CF37F2)
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(at 33.721 26.289 180)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /575B1260/57CE14A6)
(attr smd)
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(fp_text reference C306 (at 0 -2.794 180) (layer B.SilkS)
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(fp_text value 10nF (at 0 -1.9 180) (layer B.SilkS) hide
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end -1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.85 0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -0.35 0.6) (end 0.35 0.6) (layer B.SilkS) (width 0.15))
(fp_line (start 0.35 -0.6) (end -0.35 -0.6) (layer B.SilkS) (width 0.15))
(pad 1 smd rect (at -0.95 0 180) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
(net 40 /Mikrocontroller/VInSense))
(pad 2 smd rect (at 0.95 0 180) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
(net 2 GND))
(model Capacitors_SMD/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(module Capacitors_SMD:C_0603_HandSoldering (layer B.Cu) (tedit 57D1BBE9) (tstamp 57CF37F8)
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(at 43.561 54.417 90)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /575B1260/57CE188F)
(attr smd)
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(fp_text reference C307 (at 3.744 0.127 90) (layer B.SilkS)
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(fp_text value 10nF (at 0 -1.9 90) (layer B.SilkS) hide
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end -1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.85 0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -0.35 0.6) (end 0.35 0.6) (layer B.SilkS) (width 0.15))
(fp_line (start 0.35 -0.6) (end -0.35 -0.6) (layer B.SilkS) (width 0.15))
(pad 1 smd rect (at -0.95 0 90) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
(net 41 /Mikrocontroller/VOutSense))
(pad 2 smd rect (at 0.95 0 90) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
(net 2 GND))
(model Capacitors_SMD/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(module Resistors_SMD:R_0603_HandSoldering (layer F.Cu) (tedit 57D1C941) (tstamp 57CF380A)
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(at 65.786 45.931 270)
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /575B1260/57CDFBAF)
(attr smd)
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(fp_text reference R310 (at -3.894 0 270) (layer F.SilkS)
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(fp_text value 10k (at 0 1.9 270) (layer F.SilkS) hide
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -2 -0.8) (end 2 -0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end -2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 2 -0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 0.5 0.675) (end -0.5 0.675) (layer F.SilkS) (width 0.15))
(fp_line (start -0.5 -0.675) (end 0.5 -0.675) (layer F.SilkS) (width 0.15))
(pad 1 smd rect (at -1.1 0 270) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
(net 53 "Net-(R310-Pad1)"))
(pad 2 smd rect (at 1.1 0 270) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
(net 44 /Mikrocontroller/SW_on))
(model Resistors_SMD/R_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(module Resistors_SMD:R_0603_HandSoldering (layer B.Cu) (tedit 57D1C037) (tstamp 57CF3810)
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(at 56.388 20.109 270)
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /575B1260/57CE0E76)
(attr smd)
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(fp_text reference R311 (at 0.084 -1.524 270) (layer B.SilkS)
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(fp_text value 10 (at 0 -1.9 270) (layer B.SilkS) hide
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -2 0.8) (end 2 0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end 2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end -2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start 2 0.8) (end 2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start 0.5 -0.675) (end -0.5 -0.675) (layer B.SilkS) (width 0.15))
(fp_line (start -0.5 0.675) (end 0.5 0.675) (layer B.SilkS) (width 0.15))
(pad 1 smd rect (at -1.1 0 270) (size 1.2 0.9) (layers B.Cu B.Paste B.Mask)
(net 36 "Net-(Q302-Pad1)"))
(pad 2 smd rect (at 1.1 0 270) (size 1.2 0.9) (layers B.Cu B.Paste B.Mask)
(net 54 "Net-(R311-Pad2)"))
(model Resistors_SMD/R_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(module SMD_Packages:SOT-23 (layer B.Cu) (tedit 57D1BC05) (tstamp 57CF3811)
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(at 53.086 66.25082 270)
(tags SOT23)
(path /57CDE509)
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(fp_text reference U103 (at 2.20218 0 540) (layer B.SilkS)
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(fp_text value MCP1702T-3302E/CB (at 0.0635 0 270) (layer B.SilkS) hide
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_circle (center -1.17602 -0.35052) (end -1.30048 -0.44958) (layer B.SilkS) (width 0.15))
(fp_line (start 1.27 0.508) (end 1.27 -0.508) (layer B.SilkS) (width 0.15))
(fp_line (start -1.3335 0.508) (end -1.3335 -0.508) (layer B.SilkS) (width 0.15))
(fp_line (start 1.27 -0.508) (end -1.3335 -0.508) (layer B.SilkS) (width 0.15))
(fp_line (start -1.3335 0.508) (end 1.27 0.508) (layer B.SilkS) (width 0.15))
(pad 3 smd rect (at 0 1.09982 270) (size 0.8001 1.00076) (layers B.Cu B.Paste B.Mask)
(net 4 +5V))
(pad 2 smd rect (at 0.9525 -1.09982 270) (size 0.8001 1.00076) (layers B.Cu B.Paste B.Mask)
(net 5 +3V3))
(pad 1 smd rect (at -0.9525 -1.09982 270) (size 0.8001 1.00076) (layers B.Cu B.Paste B.Mask)
(net 2 GND))
(model SMD_Packages/SOT-23.wrl
(at (xyz 0 0 0))
(scale (xyz 0.4 0.4 0.4))
(rotate (xyz 0 0 180))
)
)
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(module Capacitors_SMD:C_0603_HandSoldering (layer B.Cu) (tedit 57D1BC4F) (tstamp 57CF3844)
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(at 28.300011 20.594643 270)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /57CE2990)
(attr smd)
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(fp_text reference C106 (at -0.020643 1.376011 270) (layer B.SilkS)
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(fp_text value 100nF (at 0 -1.9 270) (layer B.SilkS) hide
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end -1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.85 0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -0.35 0.6) (end 0.35 0.6) (layer B.SilkS) (width 0.15))
(fp_line (start 0.35 -0.6) (end -0.35 -0.6) (layer B.SilkS) (width 0.15))
(pad 1 smd rect (at -0.95 0 270) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
(net 13 "/Power Converter/Vpanel"))
(pad 2 smd rect (at 0.95 0 270) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
(net 2 GND))
(model Capacitors_SMD/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(module Capacitors_SMD:C_0603_HandSoldering (layer B.Cu) (tedit 57D1BC4C) (tstamp 57CF384A)
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(at 30.126945 20.594643 270)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /57CE2BDD)
(attr smd)
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(fp_text reference C107 (at 0 -1.496055 270) (layer B.SilkS)
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(fp_text value 10nF (at 0 -1.9 270) (layer B.SilkS) hide
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end -1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.85 0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -0.35 0.6) (end 0.35 0.6) (layer B.SilkS) (width 0.15))
(fp_line (start 0.35 -0.6) (end -0.35 -0.6) (layer B.SilkS) (width 0.15))
(pad 1 smd rect (at -0.95 0 270) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
(net 13 "/Power Converter/Vpanel"))
(pad 2 smd rect (at 0.95 0 270) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
(net 2 GND))
(model Capacitors_SMD/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(module Capacitors_SMD:C_0603_HandSoldering (layer B.Cu) (tedit 57D1BC13) (tstamp 57CF3850)
(at 25.273 51.877 90)
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /57CE5C63)
(attr smd)
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(fp_text reference C108 (at 0 -1.524 90) (layer B.SilkS)
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(fp_text value 100nF (at 0 -1.9 90) (layer B.SilkS) hide
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end -1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.85 0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -0.35 0.6) (end 0.35 0.6) (layer B.SilkS) (width 0.15))
(fp_line (start 0.35 -0.6) (end -0.35 -0.6) (layer B.SilkS) (width 0.15))
(pad 1 smd rect (at -0.95 0 90) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
(net 1 +BATT))
(pad 2 smd rect (at 0.95 0 90) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
(net 11 "/Power Converter/Bat-"))
(model Capacitors_SMD/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(module Capacitors_SMD:C_0603_HandSoldering (layer B.Cu) (tedit 57D1BC17) (tstamp 57CF3856)
(at 27.305 51.877 90)
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /57CE5C69)
(attr smd)
(fp_text reference C109 (at 0 1.9 90) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(fp_text value 10nF (at 0 -1.9 90) (layer B.SilkS) hide
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end -1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.85 0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -0.35 0.6) (end 0.35 0.6) (layer B.SilkS) (width 0.15))
(fp_line (start 0.35 -0.6) (end -0.35 -0.6) (layer B.SilkS) (width 0.15))
(pad 1 smd rect (at -0.95 0 90) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
(net 1 +BATT))
(pad 2 smd rect (at 0.95 0 90) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
(net 11 "/Power Converter/Bat-"))
(model Capacitors_SMD/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(module Capacitors_SMD:C_0603_HandSoldering (layer B.Cu) (tedit 57D1BC2C) (tstamp 57CF385C)
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(at 24.971665 64.184985 90)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /57CE64A7)
(attr smd)
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(fp_text reference C110 (at 0 -1.730665 90) (layer B.SilkS)
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(fp_text value 100nF (at 0 -1.9 90) (layer B.SilkS) hide
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end -1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.85 0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -0.35 0.6) (end 0.35 0.6) (layer B.SilkS) (width 0.15))
(fp_line (start 0.35 -0.6) (end -0.35 -0.6) (layer B.SilkS) (width 0.15))
(pad 1 smd rect (at -0.95 0 90) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
(net 1 +BATT))
(pad 2 smd rect (at 0.95 0 90) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
(net 14 "/Power Converter/Load-"))
(model Capacitors_SMD/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(module Capacitors_SMD:C_0603_HandSoldering (layer B.Cu) (tedit 57D1BC2F) (tstamp 57CF3862)
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(at 26.876665 64.189985 90)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /57CE64AD)
(attr smd)
(fp_text reference C111 (at 0 1.9 90) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(fp_text value 10nF (at 0 -1.9 90) (layer B.SilkS) hide
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end -1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.85 0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -0.35 0.6) (end 0.35 0.6) (layer B.SilkS) (width 0.15))
(fp_line (start 0.35 -0.6) (end -0.35 -0.6) (layer B.SilkS) (width 0.15))
(pad 1 smd rect (at -0.95 0 90) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
(net 1 +BATT))
(pad 2 smd rect (at 0.95 0 90) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
(net 14 "/Power Converter/Load-"))
(model Capacitors_SMD/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(module Connect:1pin (layer F.Cu) (tedit 57D1BFBC) (tstamp 57D075EE)
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(at 67.437 19.05)
(descr "module 1 pin (ou trou mecanique de percage)")
(tags DEV)
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(fp_text reference 1pin (at 0 -3.048) (layer F.SilkS) hide
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value VAL** (at 0 2.794) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_circle (center 0 0) (end 0 -2.286) (layer F.SilkS) (width 0.15))
(pad 1 thru_hole circle (at 0 0) (size 5 5) (drill 3.2) (layers *.Cu *.Mask F.SilkS)
(net 2 GND) (zone_connect 2))
)
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(module Diodes:Diode-SMA_PinReversed (layer B.Cu) (tedit 57D1C45C) (tstamp 57D1C61A)
(at 68.453 25.49398 90)
(descr "Diode SMA")
(tags "Diode SMA")
(path /575B1260/57CE078A)
(attr smd)
(fp_text reference D303 (at -5.49402 0.127 90) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 16V (at 0 -3.81 90) (layer B.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text user A (at -3.29946 -1.6002 90) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text user K (at 2.99974 -1.69926 90) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_circle (center 0 0) (end 0.20066 0.0508) (layer B.Adhes) (width 0.381))
(fp_line (start 1.80086 -1.75006) (end 1.80086 -1.39954) (layer B.SilkS) (width 0.15))
(fp_line (start 1.80086 1.75006) (end 1.80086 1.39954) (layer B.SilkS) (width 0.15))
(fp_line (start 2.25044 -1.75006) (end 2.25044 -1.39954) (layer B.SilkS) (width 0.15))
(fp_line (start -2.25044 -1.75006) (end -2.25044 -1.39954) (layer B.SilkS) (width 0.15))
(fp_line (start -2.25044 1.75006) (end -2.25044 1.39954) (layer B.SilkS) (width 0.15))
(fp_line (start 2.25044 1.75006) (end 2.25044 1.39954) (layer B.SilkS) (width 0.15))
(fp_line (start -2.25044 -1.75006) (end 2.25044 -1.75006) (layer B.SilkS) (width 0.15))
(fp_line (start -2.25044 1.75006) (end 2.25044 1.75006) (layer B.SilkS) (width 0.15))
(pad 2 smd rect (at -1.99898 0 90) (size 2.49936 1.80086) (layers B.Cu B.Paste B.Mask)
(net 2 GND))
(pad 1 smd rect (at 1.99898 0 90) (size 2.49936 1.80086) (layers B.Cu B.Paste B.Mask)
(net 3 +12V))
(model Diodes_SMD/Diode-SMA_Standard.wrl
(at (xyz 0 0 0))
(scale (xyz 0.3937 0.3937 0.3937))
(rotate (xyz 0 0 0))
)
)
(gr_text "SolarLader v1.1" (at 68.961 33.528 90) (layer F.SilkS)
Added C for current meas. opamp
2016-06-29 23:00:58 +02:00
(effects (font (size 1.5 1.5) (thickness 0.3)))
)
Completed routing iteration
2016-06-27 21:55:33 +02:00
(gr_text "C103 löschen?" (at 83.82 54.61) (layer Cmts.User)
(effects (font (size 1.5 1.5) (thickness 0.3)))
)
(gr_text "49.530 mm x 56.515 mm\n= 2799.188 mm²\n= 4.339 in²\n= 21.69 $" (at 74.295 20.32) (layer Cmts.User)
(effects (font (size 1.5 1.5) (thickness 0.3)) (justify left))
)
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(gr_line (start 70.739 72.39) (end 17.526 72.39) (layer Edge.Cuts) (width 0.15))
(gr_line (start 70.739 16.002) (end 70.739 72.39) (layer Edge.Cuts) (width 0.15))
(dimension 53.213 (width 0.3) (layer Cmts.User)
(gr_text "53,213 mm" (at 44.1325 6.638853) (layer Cmts.User)
Initial commit - Full schematic - Partially placed board
2016-06-26 00:26:23 +02:00
(effects (font (size 1.5 1.5) (thickness 0.3)))
)
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(feature1 (pts (xy 70.739 15.24) (xy 70.739 5.288853)))
(feature2 (pts (xy 17.526 15.24) (xy 17.526 5.288853)))
(crossbar (pts (xy 17.526 7.988853) (xy 70.739 7.988853)))
(arrow1a (pts (xy 70.739 7.988853) (xy 69.612496 8.575274)))
(arrow1b (pts (xy 70.739 7.988853) (xy 69.612496 7.402432)))
(arrow2a (pts (xy 17.526 7.988853) (xy 18.652504 8.575274)))
(arrow2b (pts (xy 17.526 7.988853) (xy 18.652504 7.402432)))
Initial commit - Full schematic - Partially placed board
2016-06-26 00:26:23 +02:00
)
Completed routing iteration
2016-06-27 21:55:33 +02:00
(dimension 56.388 (width 0.3) (layer Cmts.User)
(gr_text "56,388 mm" (at 5.645 44.196 270) (layer Cmts.User)
Initial commit - Full schematic - Partially placed board
2016-06-26 00:26:23 +02:00
(effects (font (size 1.5 1.5) (thickness 0.3)))
)
Completed routing iteration
2016-06-27 21:55:33 +02:00
(feature1 (pts (xy 16.51 72.39) (xy 4.295 72.39)))
(feature2 (pts (xy 16.51 16.002) (xy 4.295 16.002)))
(crossbar (pts (xy 6.995 16.002) (xy 6.995 72.39)))
(arrow1a (pts (xy 6.995 72.39) (xy 6.408579 71.263496)))
(arrow1b (pts (xy 6.995 72.39) (xy 7.581421 71.263496)))
(arrow2a (pts (xy 6.995 16.002) (xy 6.408579 17.128504)))
(arrow2b (pts (xy 6.995 16.002) (xy 7.581421 17.128504)))
Initial commit - Full schematic - Partially placed board
2016-06-26 00:26:23 +02:00
)
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(gr_line (start 17.526 16.002) (end 70.739 16.002) (layer Edge.Cuts) (width 0.15))
(gr_line (start 17.526 72.39) (end 17.526 16.002) (layer Edge.Cuts) (width 0.15))
Initial commit - Full schematic - Partially placed board
2016-06-26 00:26:23 +02:00
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(segment (start 25.273 52.827) (end 24.398 52.827) (width 0.5) (layer B.Cu) (net 1))
(segment (start 24.398 52.827) (end 24.002001 53.222999) (width 0.5) (layer B.Cu) (net 1))
(segment (start 24.002001 53.222999) (end 23.231001 53.222999) (width 0.5) (layer B.Cu) (net 1))
(segment (start 23.231001 53.222999) (end 28.829 53.222999) (width 2) (layer B.Cu) (net 1))
(segment (start 27.305 52.827) (end 28.18 52.827) (width 0.5) (layer B.Cu) (net 1))
(segment (start 28.829 53.222999) (end 34.172999 53.222999) (width 2) (layer B.Cu) (net 1))
(segment (start 28.18 52.827) (end 28.575999 53.222999) (width 0.5) (layer B.Cu) (net 1))
(segment (start 28.575999 53.222999) (end 28.829 53.222999) (width 0.5) (layer B.Cu) (net 1))
(segment (start 21.59 55.88) (end 21.59 54.864) (width 2) (layer B.Cu) (net 1))
(segment (start 21.59 54.864) (end 23.231001 53.222999) (width 2) (layer B.Cu) (net 1))
(segment (start 34.695131 53.745131) (end 36.195 55.245) (width 2) (layer B.Cu) (net 1))
(segment (start 34.172999 53.222999) (end 34.695131 53.745131) (width 2) (layer B.Cu) (net 1))
(segment (start 21.336 55.88) (end 20.193 55.88) (width 2) (layer B.Cu) (net 1))
(segment (start 20.193 55.88) (end 18.765999 57.307001) (width 2) (layer B.Cu) (net 1))
(segment (start 18.765999 57.307001) (end 18.765999 65.120999) (width 2) (layer B.Cu) (net 1))
(segment (start 18.765999 65.120999) (end 20.32 66.675) (width 2) (layer B.Cu) (net 1))
(segment (start 20.32 66.675) (end 21.336 66.675) (width 2) (layer B.Cu) (net 1))
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(segment (start 24.971665 65.134985) (end 23.790015 65.134985) (width 0.5) (layer B.Cu) (net 1))
(segment (start 23.790015 65.134985) (end 22.25 66.675) (width 0.5) (layer B.Cu) (net 1))
(segment (start 26.876665 65.139985) (end 24.976665 65.139985) (width 0.5) (layer B.Cu) (net 1))
(segment (start 24.976665 65.139985) (end 24.971665 65.134985) (width 0.5) (layer B.Cu) (net 1))
Added C for current meas. opamp
2016-06-29 23:00:58 +02:00
(segment (start 42.545 60.96) (end 38.882 60.96) (width 1) (layer B.Cu) (net 1))
(segment (start 38.882 60.96) (end 38.862 60.98) (width 1) (layer B.Cu) (net 1))
(segment (start 47.625 59.69) (end 43.815 59.69) (width 1) (layer B.Cu) (net 1))
(segment (start 43.815 59.69) (end 42.545 60.96) (width 1) (layer B.Cu) (net 1))
Completed routing iteration
2016-06-27 21:55:33 +02:00
(segment (start 47.625 59.69) (end 47.625 57.15) (width 0.5) (layer B.Cu) (net 1))
(segment (start 47.625 57.15) (end 48.26 56.515) (width 0.5) (layer B.Cu) (net 1))
(segment (start 36.195 55.245) (end 36.83 55.245) (width 1) (layer B.Cu) (net 1))
(segment (start 36.83 55.245) (end 42.545 60.96) (width 1) (layer B.Cu) (net 1))
(segment (start 36.195 55.245) (end 38.224778 53.215222) (width 2) (layer B.Cu) (net 1))
(segment (start 38.224778 53.215222) (end 39.924664 53.215222) (width 2) (layer B.Cu) (net 1))
(segment (start 42.048306 31.094594) (end 42.048306 35.124399) (width 2) (layer B.Cu) (net 1))
(segment (start 42.048306 35.124399) (end 39.924664 37.248041) (width 2) (layer B.Cu) (net 1))
(segment (start 39.924664 50.615222) (end 39.924664 53.215222) (width 2) (layer B.Cu) (net 1))
(segment (start 39.924664 37.248041) (end 39.924664 50.615222) (width 2) (layer B.Cu) (net 1))
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(segment (start 42 53.28) (end 42 53.25) (width 0.3) (layer B.Cu) (net 2))
(segment (start 42 53.25) (end 42.926 52.324) (width 0.3) (layer B.Cu) (net 2))
(via (at 42.926 52.324) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 2))
Final fixes before fab
2016-07-03 23:52:32 +02:00
(segment (start 36.195 41.91) (end 36.195 43.18) (width 0.3) (layer B.Cu) (net 2))
(segment (start 36.195 43.18) (end 36.703 43.688) (width 0.3) (layer B.Cu) (net 2))
(via (at 36.703 43.688) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 2))
(segment (start 58.42 36.195) (end 58.42 34.925) (width 0.3) (layer B.Cu) (net 2))
(via (at 58.42 34.925) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 2))
(segment (start 58.42 37.465) (end 58.42 36.195) (width 0.3) (layer F.Cu) (net 2))
(via (at 58.42 36.195) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 2))
(segment (start 59.69 37.465) (end 58.42 37.465) (width 0.3) (layer B.Cu) (net 2))
(via (at 58.42 37.465) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 2))
Completed routing iteration
2016-06-27 21:55:33 +02:00
(segment (start 32.604466 24.681678) (end 32.604466 28.794466) (width 0.3) (layer B.Cu) (net 2))
(segment (start 32.604466 28.794466) (end 33.02 29.21) (width 0.3) (layer B.Cu) (net 2))
(via (at 33.02 29.21) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 2))
(segment (start 32.85 46.185) (end 31.41 47.625) (width 0.3) (layer B.Cu) (net 2))
(segment (start 31.41 47.625) (end 26.035 47.625) (width 0.3) (layer B.Cu) (net 2))
(via (at 26.035 47.625) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 2))
(segment (start 32.85 43.815) (end 32.85 46.185) (width 0.3) (layer B.Cu) (net 2))
(segment (start 50.127565 58.072435) (end 49.829311 58.072435) (width 0.3) (layer B.Cu) (net 2))
(segment (start 50.76 57.44) (end 50.127565 58.072435) (width 0.3) (layer B.Cu) (net 2))
(segment (start 50.76 56.515) (end 50.76 57.44) (width 0.3) (layer B.Cu) (net 2))
(via (at 49.829311 58.072435) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 2))
(segment (start 50.165 62.23) (end 50.165 60.325) (width 0.3) (layer F.Cu) (net 2))
(segment (start 50.165 60.325) (end 50.8 59.69) (width 0.3) (layer F.Cu) (net 2))
(via (at 50.8 59.69) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 2))
(segment (start 51 44.98) (end 52.6 44.98) (width 0.3) (layer F.Cu) (net 2))
(segment (start 52.6 44.98) (end 52.705 45.085) (width 0.3) (layer F.Cu) (net 2))
(segment (start 51.435 45.085) (end 51.05 45.47) (width 0.3) (layer B.Cu) (net 2))
(segment (start 51.05 45.47) (end 51.05 46.48) (width 0.3) (layer B.Cu) (net 2))
(segment (start 52.705 45.085) (end 51.435 45.085) (width 0.3) (layer B.Cu) (net 2))
(segment (start 52.92572 46.8358) (end 52.92572 45.30572) (width 0.3) (layer F.Cu) (net 2))
(segment (start 52.92572 45.30572) (end 52.705 45.085) (width 0.3) (layer F.Cu) (net 2))
(via (at 52.705 45.085) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 2))
(segment (start 46 43.73) (end 47.54 43.73) (width 0.3) (layer B.Cu) (net 2))
(segment (start 47.54 43.73) (end 47.625 43.815) (width 0.3) (layer B.Cu) (net 2))
(via (at 47.625 43.815) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 2))
(segment (start 56.515 52.705) (end 56.515 50.8) (width 0.3) (layer F.Cu) (net 2))
(segment (start 56.515 50.8) (end 58.42 48.895) (width 0.3) (layer F.Cu) (net 2))
(via (at 58.42 48.895) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 2))
(segment (start 59.69 57.136481) (end 59.243681 57.136481) (width 0.3) (layer F.Cu) (net 2))
(segment (start 59.243681 57.136481) (end 58.5442 56.437) (width 0.3) (layer F.Cu) (net 2))
(segment (start 36.195 40.005) (end 36.195 40.64) (width 0.3) (layer F.Cu) (net 2))
(segment (start 36.195 41.91) (end 36.195 40.005) (width 0.3) (layer B.Cu) (net 2))
(via (at 36.195 40.005) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 2))
(segment (start 36.195 41.91) (end 37.465 41.91) (width 0.3) (layer B.Cu) (net 2))
(via (at 37.465 41.91) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 2))
(segment (start 59.69 37.465) (end 60.96 37.465) (width 0.3) (layer F.Cu) (net 2))
(via (at 60.96 37.465) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 2))
(segment (start 60.015 35.394594) (end 60.015 37.14) (width 0.3) (layer B.Cu) (net 2))
(segment (start 60.015 37.14) (end 59.69 37.465) (width 0.3) (layer B.Cu) (net 2))
(via (at 59.69 37.465) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 2))
(segment (start 52.07 34.29) (end 52.07 36.195) (width 0.3) (layer F.Cu) (net 2))
(via (at 52.07 36.195) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 2))
(segment (start 53.975 34.925) (end 52.705 34.925) (width 0.3) (layer B.Cu) (net 2))
(segment (start 52.705 34.925) (end 52.07 34.29) (width 0.3) (layer B.Cu) (net 2))
(via (at 52.07 34.29) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 2))
(segment (start 31.75 43.615) (end 31.75 41.6515) (width 0.3) (layer B.Cu) (net 2))
(segment (start 31.75 41.6515) (end 32.394 41.0075) (width 0.3) (layer B.Cu) (net 2))
(segment (start 32.394 41.0075) (end 33.075 41.0075) (width 0.3) (layer B.Cu) (net 2))
(segment (start 32.85 43.815) (end 31.95 43.815) (width 0.3) (layer B.Cu) (net 2))
(segment (start 31.95 43.815) (end 31.75 43.615) (width 0.3) (layer B.Cu) (net 2))
(segment (start 60.5 56.48) (end 60.346481 56.48) (width 0.3) (layer F.Cu) (net 2))
(segment (start 60.346481 56.48) (end 59.69 57.136481) (width 0.3) (layer F.Cu) (net 2))
(via (at 59.69 57.136481) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 2))
(segment (start 46 56.73) (end 44.87 56.73) (width 0.3) (layer B.Cu) (net 2))
(segment (start 44.87 56.73) (end 44.45 57.15) (width 0.3) (layer B.Cu) (net 2))
(via (at 44.45 57.15) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 2))
(segment (start 55.65 53.48) (end 55.74 53.48) (width 0.3) (layer B.Cu) (net 2))
(segment (start 55.74 53.48) (end 56.515 52.705) (width 0.3) (layer B.Cu) (net 2))
(via (at 56.515 52.705) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 2))
(segment (start 33.95 67.945) (end 34.925 67.945) (width 0.3) (layer F.Cu) (net 2))
(segment (start 34.925 67.945) (end 35.56 67.31) (width 0.3) (layer F.Cu) (net 2))
(via (at 35.56 67.31) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 2))
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(segment (start 66.675 23.495) (end 69.977 26.797) (width 0.5) (layer F.Cu) (net 3))
(segment (start 69.977 26.797) (end 69.977 41.783) (width 0.5) (layer F.Cu) (net 3))
(segment (start 69.977 41.783) (end 66.929 44.831) (width 0.5) (layer F.Cu) (net 3))
(segment (start 66.929 44.831) (end 66.929 50.673) (width 0.5) (layer F.Cu) (net 3))
(segment (start 66.929 50.673) (end 65.024 52.578) (width 0.5) (layer F.Cu) (net 3))
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(segment (start 65.024 52.578) (end 65.010305 52.578) (width 0.5) (layer F.Cu) (net 3))
(segment (start 65.010305 52.578) (end 64.248305 53.34) (width 0.5) (layer F.Cu) (net 3))
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(segment (start 64.248305 53.34) (end 64.248305 57.023) (width 0.5) (layer F.Cu) (net 3))
(segment (start 62.597305 58.674) (end 58.841 58.674) (width 0.5) (layer F.Cu) (net 3))
(segment (start 64.248305 57.023) (end 62.597305 58.674) (width 0.5) (layer F.Cu) (net 3))
(segment (start 58.841 58.674) (end 57.19 60.325) (width 0.5) (layer F.Cu) (net 3))
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(segment (start 68.453 23.495) (end 66.675 23.495) (width 0.5) (layer B.Cu) (net 3))
(segment (start 66.675 23.495) (end 65.639 23.495) (width 0.5) (layer B.Cu) (net 3))
(via (at 66.675 23.495) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 3))
(segment (start 64.77 23.495) (end 65.639 23.495) (width 0.5) (layer B.Cu) (net 3))
(segment (start 65.639 23.495) (end 65.913 23.769) (width 0.5) (layer B.Cu) (net 3))
(segment (start 65.913 23.769) (end 65.913 25.019) (width 0.5) (layer B.Cu) (net 3))
Completed routing iteration
2016-06-27 21:55:33 +02:00
(segment (start 64.77 23.495) (end 63.275 23.495) (width 0.5) (layer B.Cu) (net 3))
(segment (start 63.275 23.495) (end 63.27 23.5) (width 0.5) (layer B.Cu) (net 3))
(segment (start 52.705 59.69) (end 56.555 59.69) (width 0.5) (layer B.Cu) (net 3))
(segment (start 56.555 59.69) (end 57.19 60.325) (width 0.5) (layer B.Cu) (net 3))
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(segment (start 49.53 64.897) (end 49.53 65.847) (width 0.3) (layer B.Cu) (net 4))
(segment (start 49.53 65.847) (end 49.93382 66.25082) (width 0.3) (layer B.Cu) (net 4))
(segment (start 49.93382 66.25082) (end 51.98618 66.25082) (width 0.3) (layer B.Cu) (net 4))
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(segment (start 42.545 66.04) (end 46.228 66.04) (width 0.3) (layer B.Cu) (net 4))
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(segment (start 46.228 66.04) (end 47.371 64.897) (width 0.3) (layer B.Cu) (net 4))
(segment (start 47.371 64.897) (end 49.53 64.897) (width 0.3) (layer B.Cu) (net 4))
Completed routing iteration
2016-06-27 21:55:33 +02:00
(segment (start 32.692998 66.04) (end 40.975 66.04) (width 0.3) (layer B.Cu) (net 4))
(segment (start 30.152998 68.58) (end 32.692998 66.04) (width 0.3) (layer B.Cu) (net 4))
(segment (start 25.0876 68.58) (end 30.152998 68.58) (width 0.3) (layer B.Cu) (net 4))
(segment (start 22.84 70.8276) (end 25.0876 68.58) (width 0.3) (layer B.Cu) (net 4))
(segment (start 22.84 70.98) (end 22.84 70.8276) (width 0.3) (layer B.Cu) (net 4))
(segment (start 40.975 66.04) (end 42.545 66.04) (width 0.3) (layer B.Cu) (net 4))
(segment (start 27.305 67.945) (end 25.7226 67.945) (width 0.3) (layer F.Cu) (net 4))
(segment (start 25.7226 67.945) (end 22.84 70.8276) (width 0.3) (layer F.Cu) (net 4))
(segment (start 22.84 70.8276) (end 22.84 70.98) (width 0.3) (layer F.Cu) (net 4))
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(segment (start 56.769 64.897) (end 56.769 64.328) (width 0.3) (layer F.Cu) (net 5))
(segment (start 56.769 64.328) (end 56.054541 63.613541) (width 0.3) (layer F.Cu) (net 5))
(segment (start 56.054541 59.530457) (end 57.798507 57.786491) (width 0.3) (layer F.Cu) (net 5))
(segment (start 56.054541 63.613541) (end 56.054541 59.530457) (width 0.3) (layer F.Cu) (net 5))
(segment (start 57.798507 57.786491) (end 60.868509 57.786491) (width 0.3) (layer F.Cu) (net 5))
(segment (start 60.868509 57.786491) (end 62.175 56.48) (width 0.3) (layer F.Cu) (net 5))
(segment (start 62.175 56.48) (end 62.4 56.48) (width 0.3) (layer F.Cu) (net 5))
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(segment (start 66.675 71.12) (end 66.421 71.12) (width 0.3) (layer B.Cu) (net 5))
(segment (start 66.421 71.12) (end 62.202998 71.12) (width 0.3) (layer B.Cu) (net 5))
(segment (start 68.407 71.12) (end 66.421 71.12) (width 0.3) (layer B.Cu) (net 5))
(segment (start 56.769 65.278) (end 58.039 65.278) (width 0.3) (layer B.Cu) (net 5))
(segment (start 59.182 68.099002) (end 59.182 66.421) (width 0.3) (layer B.Cu) (net 5))
(segment (start 59.182 66.421) (end 58.039 65.278) (width 0.3) (layer B.Cu) (net 5))
(segment (start 62.202998 71.12) (end 59.182 68.099002) (width 0.3) (layer B.Cu) (net 5))
(segment (start 54.18582 67.20332) (end 54.28615 67.20332) (width 0.3) (layer B.Cu) (net 5))
(segment (start 54.28615 67.20332) (end 56.21147 65.278) (width 0.3) (layer B.Cu) (net 5))
(segment (start 56.21147 65.278) (end 56.769 65.278) (width 0.3) (layer B.Cu) (net 5))
Added C for current meas. opamp
2016-06-29 23:00:58 +02:00
(segment (start 29.529999 39.177001) (end 28.809 39.898) (width 0.3) (layer B.Cu) (net 5))
(segment (start 28.809 39.898) (end 27.813 39.898) (width 0.3) (layer B.Cu) (net 5))
(segment (start 29.529999 39.176999) (end 29.529999 39.177001) (width 0.3) (layer B.Cu) (net 5))
Completed routing iteration
2016-06-27 21:55:33 +02:00
(segment (start 38.399999 44.785001) (end 38.1 45.085) (width 0.3) (layer B.Cu) (net 5))
(segment (start 38.399999 41.247995) (end 38.399999 44.785001) (width 0.3) (layer B.Cu) (net 5))
(segment (start 36.507002 39.354998) (end 38.399999 41.247995) (width 0.3) (layer B.Cu) (net 5))
(segment (start 35.882998 39.354998) (end 36.507002 39.354998) (width 0.3) (layer B.Cu) (net 5))
(segment (start 33.827999 37.299999) (end 35.882998 39.354998) (width 0.3) (layer B.Cu) (net 5))
(segment (start 29.599999 37.299999) (end 33.827999 37.299999) (width 0.3) (layer B.Cu) (net 5))
(segment (start 29.529999 39.176999) (end 29.529999 37.369999) (width 0.3) (layer B.Cu) (net 5))
(segment (start 30.535 40.055) (end 30.408 40.055) (width 0.3) (layer B.Cu) (net 5))
(segment (start 30.408 40.055) (end 29.529999 39.176999) (width 0.3) (layer B.Cu) (net 5))
(segment (start 29.529999 37.369999) (end 29.599999 37.299999) (width 0.3) (layer B.Cu) (net 5))
(via (at 53.35228 51.574408) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 5))
(segment (start 53.75 51.972128) (end 53.652279 51.874407) (width 0.3) (layer B.Cu) (net 5))
(segment (start 58.568801 55.087509) (end 56.865381 55.087509) (width 0.3) (layer F.Cu) (net 5))
(segment (start 52.888968 52.03772) (end 53.052281 51.874407) (width 0.3) (layer F.Cu) (net 5))
(segment (start 53.652279 50.255749) (end 53.652279 51.274409) (width 0.3) (layer F.Cu) (net 5))
(segment (start 56.865381 55.087509) (end 53.652279 51.874407) (width 0.3) (layer F.Cu) (net 5))
(segment (start 59.20051 54.4558) (end 58.568801 55.087509) (width 0.3) (layer F.Cu) (net 5))
(segment (start 53.652279 51.874407) (end 53.35228 51.574408) (width 0.3) (layer F.Cu) (net 5))
(segment (start 53.052281 51.874407) (end 53.35228 51.574408) (width 0.3) (layer F.Cu) (net 5))
(segment (start 55.245 51.435) (end 53.491688 51.435) (width 0.3) (layer B.Cu) (net 5))
(segment (start 60.5 54.4558) (end 59.20051 54.4558) (width 0.3) (layer F.Cu) (net 5))
(segment (start 50.93436 52.03772) (end 52.888968 52.03772) (width 0.3) (layer F.Cu) (net 5))
(segment (start 53.491688 51.435) (end 53.35228 51.574408) (width 0.3) (layer B.Cu) (net 5))
(segment (start 53.75 53.48) (end 53.75 51.972128) (width 0.3) (layer B.Cu) (net 5))
(segment (start 53.652279 51.874407) (end 53.35228 51.574408) (width 0.3) (layer B.Cu) (net 5))
(segment (start 50.93436 48.83732) (end 52.23385 48.83732) (width 0.3) (layer F.Cu) (net 5))
(segment (start 52.23385 48.83732) (end 53.652279 50.255749) (width 0.3) (layer F.Cu) (net 5))
(segment (start 53.652279 51.274409) (end 53.35228 51.574408) (width 0.3) (layer F.Cu) (net 5))
(segment (start 38.1 45.085) (end 49.43 45.085) (width 0.3) (layer F.Cu) (net 5))
(segment (start 49.43 45.085) (end 51 46.655) (width 0.3) (layer F.Cu) (net 5))
(segment (start 51 46.655) (end 51 46.88) (width 0.3) (layer F.Cu) (net 5))
(via (at 38.1 45.085) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 5))
(segment (start 51 46.88) (end 51 48.77168) (width 0.3) (layer F.Cu) (net 5))
(segment (start 51 48.77168) (end 50.93436 48.83732) (width 0.3) (layer F.Cu) (net 5))
(segment (start 62.0758 54.4558) (end 62.4 54.78) (width 0.3) (layer F.Cu) (net 5))
(segment (start 62.4 54.78) (end 62.4 56.48) (width 0.3) (layer F.Cu) (net 5))
(segment (start 60.5 54.4558) (end 62.0758 54.4558) (width 0.3) (layer F.Cu) (net 5))
(segment (start 46 47.73) (end 46 45.63) (width 0.3) (layer B.Cu) (net 6))
(segment (start 50.93436 49.63742) (end 47.90742 49.63742) (width 0.3) (layer F.Cu) (net 6))
(segment (start 47.90742 49.63742) (end 46 47.73) (width 0.3) (layer F.Cu) (net 6))
(segment (start 46 54.83) (end 46 52.61188) (width 0.3) (layer B.Cu) (net 7))
(segment (start 50.93436 50.43752) (end 48.17436 50.43752) (width 0.3) (layer F.Cu) (net 7))
(segment (start 48.17436 50.43752) (end 46 52.61188) (width 0.3) (layer F.Cu) (net 7))
(segment (start 63.5 26.67) (end 63.5 25.40005) (width 0.3) (layer B.Cu) (net 8))
(segment (start 63.5 25.40005) (end 62 23.90005) (width 0.3) (layer B.Cu) (net 8))
(segment (start 62 23.90005) (end 62 23.5) (width 0.3) (layer B.Cu) (net 8))
(segment (start 54.9275 32.72536) (end 56.32755 32.72536) (width 1) (layer B.Cu) (net 9))
(segment (start 56.32755 32.72536) (end 56.9 32.15291) (width 1) (layer B.Cu) (net 9))
(segment (start 56.9 32.15291) (end 56.9 31.094594) (width 1) (layer B.Cu) (net 9))
(segment (start 61 26.67) (end 61 31.094594) (width 0.5) (layer B.Cu) (net 9))
(segment (start 61 26.67) (end 59.46 25.13) (width 0.5) (layer B.Cu) (net 9))
(segment (start 59.46 25.13) (end 59.46 23.5) (width 0.5) (layer B.Cu) (net 9))
(segment (start 61 31.094594) (end 56.9 31.094594) (width 2) (layer B.Cu) (net 9))
(segment (start 56.9 31.094594) (end 53.5 27.694594) (width 2) (layer B.Cu) (net 9))
(segment (start 53.5 27.694594) (end 53.5 23.572) (width 2) (layer B.Cu) (net 9))
(segment (start 66.048306 31.094594) (end 61 31.094594) (width 2) (layer B.Cu) (net 9))
(segment (start 38.807415 22.072097) (end 46.363903 22.072097) (width 2) (layer B.Cu) (net 10))
(segment (start 46.363903 22.072097) (end 47.15 21.286) (width 2) (layer B.Cu) (net 10))
(segment (start 39.079466 24.681678) (end 39.079466 22.344148) (width 2) (layer B.Cu) (net 10))
(segment (start 39.079466 22.344148) (end 38.807415 22.072097) (width 2) (layer B.Cu) (net 10))
(segment (start 36.455 37.465) (end 39.079466 34.840534) (width 2) (layer B.Cu) (net 10))
(segment (start 39.079466 34.840534) (end 39.079466 24.681678) (width 2) (layer B.Cu) (net 10))
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(segment (start 27.305 50.927) (end 27.305 50.165) (width 0.5) (layer B.Cu) (net 11))
(segment (start 25.273 50.927) (end 25.273 50.165) (width 0.5) (layer B.Cu) (net 11))
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(segment (start 36.195 50.165) (end 27.305 50.165) (width 2) (layer B.Cu) (net 11))
(segment (start 27.305 50.165) (end 25.273 50.165) (width 2) (layer B.Cu) (net 11))
(segment (start 25.273 50.165) (end 22.885 50.165) (width 2) (layer B.Cu) (net 11))
Completed routing iteration
2016-06-27 21:55:33 +02:00
(segment (start 36.195 45.91) (end 36.195 45.76) (width 0.5) (layer B.Cu) (net 11))
(segment (start 36.195 45.76) (end 34.794999 44.359999) (width 0.5) (layer B.Cu) (net 11))
(segment (start 34.794999 44.359999) (end 34.794999 43.552999) (width 0.5) (layer B.Cu) (net 11))
(segment (start 34.794999 43.552999) (end 33.202 41.96) (width 0.5) (layer B.Cu) (net 11))
(segment (start 33.202 41.96) (end 33.075 41.96) (width 0.5) (layer B.Cu) (net 11))
(segment (start 36.195 50.165) (end 36.195 45.91) (width 2) (layer B.Cu) (net 11))
(segment (start 22.885 50.165) (end 22.25 50.8) (width 2) (layer B.Cu) (net 11))
(segment (start 36.83 61.214) (end 36.1315 61.214) (width 2) (layer F.Cu) (net 11))
(segment (start 36.1315 61.214) (end 33.395129 58.477629) (width 2) (layer F.Cu) (net 11))
(segment (start 33.395129 58.477629) (end 33.395129 52.964871) (width 2) (layer F.Cu) (net 11))
(segment (start 33.395129 52.964871) (end 34.695131 51.664869) (width 2) (layer F.Cu) (net 11))
(segment (start 34.695131 51.664869) (end 36.195 50.165) (width 2) (layer F.Cu) (net 11))
(segment (start 29 25) (end 29 29.42) (width 2) (layer B.Cu) (net 12))
(segment (start 29 29.42) (end 20.955 37.465) (width 2) (layer B.Cu) (net 12))
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(segment (start 24.257 20.066) (end 26.943 17.38) (width 2) (layer B.Cu) (net 13))
(segment (start 26.943 17.38) (end 29 17.38) (width 2) (layer B.Cu) (net 13))
(segment (start 24.257 21.209) (end 24.257 20.066) (width 2) (layer B.Cu) (net 13))
(segment (start 21.336 24.13) (end 24.257 21.209) (width 2) (layer B.Cu) (net 13))
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(segment (start 28.300011 19.644643) (end 28.300011 18.079989) (width 0.5) (layer B.Cu) (net 13))
(segment (start 28.300011 18.079989) (end 29 17.38) (width 0.5) (layer B.Cu) (net 13))
(segment (start 30.126945 19.644643) (end 30.126945 18.506945) (width 0.5) (layer B.Cu) (net 13))
(segment (start 30.126945 18.506945) (end 29 17.38) (width 0.5) (layer B.Cu) (net 13))
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(segment (start 30.48 63.5) (end 23.495 63.5) (width 2) (layer F.Cu) (net 14))
(segment (start 23.495 63.5) (end 21.59 61.595) (width 2) (layer F.Cu) (net 14))
(segment (start 24.971665 63.234985) (end 23.229985 63.234985) (width 0.5) (layer B.Cu) (net 14))
(segment (start 23.229985 63.234985) (end 21.59 61.595) (width 0.5) (layer B.Cu) (net 14))
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(segment (start 26.876665 63.239985) (end 24.976665 63.239985) (width 0.5) (layer B.Cu) (net 14))
(segment (start 24.976665 63.239985) (end 24.971665 63.234985) (width 0.5) (layer B.Cu) (net 14))
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(segment (start 68.453 48.26) (end 67.737 48.26) (width 0.3) (layer B.Cu) (net 15))
(segment (start 67.737 48.26) (end 63.927 44.45) (width 0.3) (layer B.Cu) (net 15))
(segment (start 63.927 44.45) (end 62.23 44.45) (width 0.3) (layer B.Cu) (net 15))
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(via (at 62.23 44.45) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 15))
Completed routing iteration
2016-06-27 21:55:33 +02:00
(segment (start 55.32348 46.8358) (end 55.32348 45.53631) (width 0.3) (layer F.Cu) (net 15))
(segment (start 55.32348 45.53631) (end 56.40979 44.45) (width 0.3) (layer F.Cu) (net 15))
(segment (start 56.40979 44.45) (end 62.23 44.45) (width 0.3) (layer F.Cu) (net 15))
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(segment (start 66.675 50.8) (end 68.453 50.8) (width 0.3) (layer B.Cu) (net 16))
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(segment (start 60.96 43.79999) (end 61.259999 44.099989) (width 0.3) (layer B.Cu) (net 16))
(segment (start 61.295001 45.420001) (end 66.675 50.8) (width 0.3) (layer B.Cu) (net 16))
(segment (start 61.259999 44.099989) (end 61.295001 44.099989) (width 0.3) (layer B.Cu) (net 16))
(segment (start 61.295001 44.099989) (end 61.295001 45.420001) (width 0.3) (layer B.Cu) (net 16))
Completed routing iteration
2016-06-27 21:55:33 +02:00
(segment (start 56.26224 43.79999) (end 60.96 43.79999) (width 0.3) (layer F.Cu) (net 16))
(via (at 60.96 43.79999) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 16))
(segment (start 54.52592 46.8358) (end 54.52592 45.53631) (width 0.3) (layer F.Cu) (net 16))
(segment (start 54.52592 45.53631) (end 56.26224 43.79999) (width 0.3) (layer F.Cu) (net 16))
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(segment (start 69.723 46.613998) (end 66.258991 43.149989) (width 0.3) (layer B.Cu) (net 17))
(segment (start 68.961 68.58) (end 69.723 67.818) (width 0.3) (layer B.Cu) (net 17))
(segment (start 69.723 46.613998) (end 69.723 67.818) (width 0.3) (layer B.Cu) (net 17))
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(segment (start 66.258991 43.149989) (end 60.647999 43.149989) (width 0.3) (layer B.Cu) (net 17))
(segment (start 60.647999 43.149989) (end 60.309999 43.487989) (width 0.3) (layer B.Cu) (net 17))
(segment (start 60.309999 43.487989) (end 60.309999 46.355009) (width 0.3) (layer B.Cu) (net 17))
(segment (start 60.309999 46.355009) (end 62.84999 48.895) (width 0.3) (layer B.Cu) (net 17))
Completed routing iteration
2016-06-27 21:55:33 +02:00
(segment (start 60.5 48.8424) (end 62.79739 48.8424) (width 0.3) (layer F.Cu) (net 17))
(segment (start 62.79739 48.8424) (end 62.84999 48.895) (width 0.3) (layer F.Cu) (net 17))
(via (at 62.84999 48.895) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 17))
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(segment (start 66.675 63.5) (end 68.453 63.5) (width 0.3) (layer B.Cu) (net 18))
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(segment (start 65.405 53.975) (end 65.405 52.72001) (width 0.3) (layer B.Cu) (net 18))
(segment (start 65.405 52.72001) (end 63.48499 50.8) (width 0.3) (layer B.Cu) (net 18))
(segment (start 65.405 60.96) (end 65.405 53.975) (width 0.3) (layer F.Cu) (net 18))
(via (at 65.405 53.975) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 18))
(segment (start 66.675 63.5) (end 65.405 62.23) (width 0.3) (layer B.Cu) (net 18))
(segment (start 65.405 62.23) (end 65.405 60.96) (width 0.3) (layer B.Cu) (net 18))
Completed routing iteration
2016-06-27 21:55:33 +02:00
(segment (start 62.84999 50.165) (end 62.31479 49.6298) (width 0.3) (layer F.Cu) (net 18))
(segment (start 62.31479 49.6298) (end 60.5 49.6298) (width 0.3) (layer F.Cu) (net 18))
(segment (start 63.48499 50.8) (end 62.84999 50.165) (width 0.3) (layer B.Cu) (net 18))
(via (at 62.84999 50.165) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 18))
(via (at 65.405 60.96) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 18))
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(segment (start 66.675 60.96) (end 68.453 60.96) (width 0.3) (layer B.Cu) (net 19))
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(segment (start 56.530001 50.670001) (end 55.245 49.385) (width 0.3) (layer B.Cu) (net 19))
(segment (start 66.675 60.96) (end 65.420002 59.705002) (width 0.3) (layer B.Cu) (net 19))
(segment (start 59.489205 53.355001) (end 58.127003 53.355001) (width 0.3) (layer B.Cu) (net 19))
(segment (start 65.420002 59.705002) (end 63.187998 59.705002) (width 0.3) (layer B.Cu) (net 19))
(segment (start 63.187998 59.705002) (end 61.595 58.112004) (width 0.3) (layer B.Cu) (net 19))
(segment (start 58.127003 53.355001) (end 56.530001 51.757999) (width 0.3) (layer B.Cu) (net 19))
(segment (start 61.595 58.112004) (end 61.595 54.61) (width 0.3) (layer B.Cu) (net 19))
(segment (start 61.595 54.61) (end 63.515002 52.689998) (width 0.3) (layer B.Cu) (net 19))
(segment (start 61.424208 51.419998) (end 59.489205 53.355001) (width 0.3) (layer B.Cu) (net 19))
(segment (start 56.530001 51.757999) (end 56.530001 50.670001) (width 0.3) (layer B.Cu) (net 19))
(segment (start 63.515002 52.689998) (end 63.515002 51.757998) (width 0.3) (layer B.Cu) (net 19))
(segment (start 63.515002 51.757998) (end 63.177002 51.419998) (width 0.3) (layer B.Cu) (net 19))
(segment (start 63.177002 51.419998) (end 61.424208 51.419998) (width 0.3) (layer B.Cu) (net 19))
Completed routing iteration
2016-06-27 21:55:33 +02:00
(segment (start 52.70226 51.080052) (end 53.002259 50.780053) (width 0.3) (layer F.Cu) (net 19))
(segment (start 53.849947 50.780053) (end 53.426523 50.780053) (width 0.3) (layer B.Cu) (net 19))
(segment (start 55.245 49.385) (end 53.849947 50.780053) (width 0.3) (layer B.Cu) (net 19))
(segment (start 55.245 49.235) (end 55.245 49.385) (width 0.3) (layer B.Cu) (net 19))
(segment (start 50.93436 51.23762) (end 52.544692 51.23762) (width 0.3) (layer F.Cu) (net 19))
(segment (start 52.544692 51.23762) (end 52.70226 51.080052) (width 0.3) (layer F.Cu) (net 19))
(via (at 53.002259 50.780053) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 19))
(segment (start 53.426523 50.780053) (end 53.002259 50.780053) (width 0.3) (layer B.Cu) (net 19))
(segment (start 29.505 67.945) (end 29.086297 67.945) (width 0.3) (layer F.Cu) (net 21))
(segment (start 29.086297 67.945) (end 27.367297 69.664) (width 0.3) (layer F.Cu) (net 21))
(segment (start 27.367297 69.664) (end 26.5436 69.664) (width 0.3) (layer F.Cu) (net 21))
(segment (start 25.38 70.8276) (end 25.38 70.98) (width 0.3) (layer F.Cu) (net 21))
(segment (start 26.5436 69.664) (end 25.38 70.8276) (width 0.3) (layer F.Cu) (net 21))
(segment (start 31.75 67.945) (end 29.505 67.945) (width 0.3) (layer F.Cu) (net 21))
Added C for current meas. opamp
2016-06-29 23:00:58 +02:00
(segment (start 47.167893 61.175296) (end 46.743629 61.175296) (width 0.3) (layer B.Cu) (net 22))
(segment (start 48.280403 60.8805) (end 47.985607 61.175296) (width 0.3) (layer B.Cu) (net 22))
(segment (start 55.815498 60.8805) (end 48.280403 60.8805) (width 0.3) (layer B.Cu) (net 22))
(segment (start 47.985607 61.175296) (end 47.167893 61.175296) (width 0.3) (layer B.Cu) (net 22))
(segment (start 58.190001 56.744999) (end 58.190001 61.255001) (width 0.3) (layer B.Cu) (net 22))
(segment (start 62.865 52.07) (end 58.190001 56.744999) (width 0.3) (layer B.Cu) (net 22))
(segment (start 46.743629 61.59956) (end 46.743629 61.175296) (width 0.3) (layer F.Cu) (net 22))
(segment (start 56.259999 61.325001) (end 55.815498 60.8805) (width 0.3) (layer B.Cu) (net 22))
(segment (start 46.743629 64.0272) (end 46.743629 61.59956) (width 0.3) (layer F.Cu) (net 22))
(segment (start 58.120001 61.325001) (end 56.259999 61.325001) (width 0.3) (layer B.Cu) (net 22))
(segment (start 42.825829 67.945) (end 46.743629 64.0272) (width 0.3) (layer F.Cu) (net 22))
(segment (start 36.83 67.945) (end 42.825829 67.945) (width 0.3) (layer F.Cu) (net 22))
(segment (start 58.190001 61.255001) (end 58.120001 61.325001) (width 0.3) (layer B.Cu) (net 22))
(via (at 46.743629 61.175296) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 22))
Completed routing iteration
2016-06-27 21:55:33 +02:00
(segment (start 62.865 52.07) (end 62.865 51.50811) (width 0.3) (layer F.Cu) (net 22))
(segment (start 62.865 51.50811) (end 61.79949 50.4426) (width 0.3) (layer F.Cu) (net 22))
(segment (start 61.79949 50.4426) (end 60.5 50.4426) (width 0.3) (layer F.Cu) (net 22))
(via (at 62.865 52.07) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 22))
(segment (start 30.48 69.215) (end 35.56 69.215) (width 0.3) (layer B.Cu) (net 22))
(segment (start 35.56 69.215) (end 36.83 67.945) (width 0.3) (layer B.Cu) (net 22))
(via (at 36.83 67.945) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 22))
(segment (start 27.92 70.98) (end 27.92 70.8276) (width 0.3) (layer F.Cu) (net 22))
(segment (start 27.92 70.8276) (end 29.5326 69.215) (width 0.3) (layer F.Cu) (net 22))
(segment (start 29.5326 69.215) (end 30.48 69.215) (width 0.3) (layer F.Cu) (net 22))
(via (at 30.48 69.215) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 22))
(segment (start 30.46 70.8276) (end 30.46 70.98) (width 0.3) (layer F.Cu) (net 23))
(segment (start 32.542599 68.745001) (end 30.46 70.8276) (width 0.3) (layer F.Cu) (net 23))
(segment (start 47.490011 62.364989) (end 47.490011 63.98794) (width 0.3) (layer F.Cu) (net 23))
(segment (start 42.73295 68.745001) (end 32.542599 68.745001) (width 0.3) (layer F.Cu) (net 23))
(segment (start 47.490011 63.98794) (end 42.73295 68.745001) (width 0.3) (layer F.Cu) (net 23))
(segment (start 50.280887 58.539987) (end 49.0745 59.746374) (width 0.3) (layer F.Cu) (net 23))
(segment (start 52.07 57.785) (end 51.315013 58.539987) (width 0.3) (layer F.Cu) (net 23))
(segment (start 51.315013 58.539987) (end 50.280887 58.539987) (width 0.3) (layer F.Cu) (net 23))
(segment (start 49.0745 60.7805) (end 47.490011 62.364989) (width 0.3) (layer F.Cu) (net 23))
(segment (start 49.0745 59.746374) (end 49.0745 60.7805) (width 0.3) (layer F.Cu) (net 23))
(segment (start 57.785 53.975) (end 53.975 57.785) (width 0.3) (layer B.Cu) (net 23))
(segment (start 53.975 57.785) (end 52.07 57.785) (width 0.3) (layer B.Cu) (net 23))
(via (at 52.07 57.785) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 23))
(segment (start 60.5 51.23) (end 58.496638 51.23) (width 0.3) (layer F.Cu) (net 23))
(segment (start 58.496638 51.23) (end 57.551819 52.174819) (width 0.3) (layer F.Cu) (net 23))
(segment (start 57.551819 52.174819) (end 57.551819 53.741819) (width 0.3) (layer F.Cu) (net 23))
(segment (start 57.551819 53.741819) (end 57.785 53.975) (width 0.3) (layer F.Cu) (net 23))
(via (at 57.785 53.975) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 23))
(segment (start 51.549627 59.039998) (end 52.154605 58.43502) (width 0.3) (layer F.Cu) (net 24))
(segment (start 50.487998 59.039998) (end 51.549627 59.039998) (width 0.3) (layer F.Cu) (net 24))
(segment (start 47.990022 64.195051) (end 47.990022 62.599603) (width 0.3) (layer F.Cu) (net 24))
(segment (start 52.154605 58.43502) (end 52.280736 58.43502) (width 0.3) (layer F.Cu) (net 24))
(segment (start 42.940061 69.245012) (end 47.990022 64.195051) (width 0.3) (layer F.Cu) (net 24))
(segment (start 33 70.8276) (end 34.582588 69.245012) (width 0.3) (layer F.Cu) (net 24))
(segment (start 34.582588 69.245012) (end 42.940061 69.245012) (width 0.3) (layer F.Cu) (net 24))
(segment (start 52.280736 58.43502) (end 52.705 58.43502) (width 0.3) (layer F.Cu) (net 24))
(segment (start 33 70.98) (end 33 70.8276) (width 0.3) (layer F.Cu) (net 24))
(segment (start 49.574511 61.015114) (end 49.574511 59.953485) (width 0.3) (layer F.Cu) (net 24))
(segment (start 49.574511 59.953485) (end 50.487998 59.039998) (width 0.3) (layer F.Cu) (net 24))
(segment (start 47.990022 62.599603) (end 49.574511 61.015114) (width 0.3) (layer F.Cu) (net 24))
(segment (start 61.27125 52.07924) (end 61.695514 52.07924) (width 0.3) (layer F.Cu) (net 24))
(segment (start 55.339734 58.43502) (end 61.395515 52.379239) (width 0.3) (layer B.Cu) (net 24))
(segment (start 52.705 58.43502) (end 55.339734 58.43502) (width 0.3) (layer B.Cu) (net 24))
(via (at 61.695514 52.07924) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 24))
(segment (start 60.53644 52.07924) (end 61.27125 52.07924) (width 0.3) (layer F.Cu) (net 24))
(segment (start 61.395515 52.379239) (end 61.695514 52.07924) (width 0.3) (layer B.Cu) (net 24))
(segment (start 60.5 52.0428) (end 60.53644 52.07924) (width 0.3) (layer F.Cu) (net 24))
(via (at 52.705 58.43502) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 24))
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(segment (start 50.700375 67.706627) (end 50.700375 63.5) (width 0.3) (layer F.Cu) (net 29))
(segment (start 45.7 70.98) (end 45.7 69.664) (width 0.3) (layer F.Cu) (net 29))
(segment (start 50.700375 63.5) (end 54.0545 60.145875) (width 0.3) (layer F.Cu) (net 29))
(segment (start 45.7 69.664) (end 46.712999 68.651001) (width 0.3) (layer F.Cu) (net 29))
(segment (start 46.712999 68.651001) (end 49.756001 68.651001) (width 0.3) (layer F.Cu) (net 29))
(segment (start 49.756001 68.651001) (end 50.700375 67.706627) (width 0.3) (layer F.Cu) (net 29))
Completed routing iteration
2016-06-27 21:55:33 +02:00
(segment (start 54.0545 60.145875) (end 54.0545 59.234125) (width 0.3) (layer F.Cu) (net 29))
(segment (start 53.7182 58.897825) (end 53.7182 56.437) (width 0.3) (layer F.Cu) (net 29))
(segment (start 54.0545 59.234125) (end 53.7182 58.897825) (width 0.3) (layer F.Cu) (net 29))
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(segment (start 51.280497 67.939503) (end 51.280497 63.627) (width 0.3) (layer F.Cu) (net 30))
(segment (start 49.556 69.664) (end 51.280497 67.939503) (width 0.3) (layer F.Cu) (net 30))
(segment (start 49.4036 69.664) (end 49.556 69.664) (width 0.3) (layer F.Cu) (net 30))
(segment (start 54.531 57.73649) (end 54.531 56.437) (width 0.3) (layer F.Cu) (net 30))
(segment (start 48.24 70.98) (end 48.24 70.8276) (width 0.3) (layer F.Cu) (net 30))
(segment (start 54.55451 57.76) (end 54.531 57.73649) (width 0.3) (layer F.Cu) (net 30))
(segment (start 51.280497 63.627) (end 54.55451 60.352987) (width 0.3) (layer F.Cu) (net 30))
(segment (start 48.24 70.8276) (end 49.4036 69.664) (width 0.3) (layer F.Cu) (net 30))
(segment (start 54.55451 60.352987) (end 54.55451 57.76) (width 0.3) (layer F.Cu) (net 30))
(segment (start 55.054521 58.819904) (end 55.3184 58.556025) (width 0.3) (layer F.Cu) (net 31))
(segment (start 55.05452 60.659724) (end 55.054521 58.819904) (width 0.3) (layer F.Cu) (net 31))
(segment (start 51.9436 63.770644) (end 55.05452 60.659724) (width 0.3) (layer F.Cu) (net 31))
(segment (start 55.3184 57.73649) (end 55.3184 56.437) (width 0.3) (layer F.Cu) (net 31))
(segment (start 50.78 70.8276) (end 51.9436 69.664) (width 0.3) (layer F.Cu) (net 31))
(segment (start 50.78 70.98) (end 50.78 70.8276) (width 0.3) (layer F.Cu) (net 31))
(segment (start 55.3184 58.556025) (end 55.3184 57.73649) (width 0.3) (layer F.Cu) (net 31))
(segment (start 51.9436 69.664) (end 51.9436 63.770644) (width 0.3) (layer F.Cu) (net 31))
Completed routing iteration
2016-06-27 21:55:33 +02:00
(segment (start 55.554531 59.323347) (end 55.55453 60.866836) (width 0.3) (layer F.Cu) (net 32))
(segment (start 56.1058 58.772078) (end 55.554531 59.323347) (width 0.3) (layer F.Cu) (net 32))
(segment (start 53.32 63.101366) (end 53.32 69.664) (width 0.3) (layer F.Cu) (net 32))
(segment (start 55.55453 60.866836) (end 53.32 63.101366) (width 0.3) (layer F.Cu) (net 32))
(segment (start 56.1058 56.437) (end 56.1058 58.772078) (width 0.3) (layer F.Cu) (net 32))
(segment (start 53.32 69.664) (end 53.32 70.98) (width 0.3) (layer F.Cu) (net 32))
(segment (start 55.88 37.465) (end 55.88 34.925) (width 0.3) (layer B.Cu) (net 35))
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(segment (start 56.388 19.009) (end 53.509 19.009) (width 0.3) (layer B.Cu) (net 36))
(segment (start 53.509 19.009) (end 53.5 19) (width 0.3) (layer B.Cu) (net 36))
Completed routing iteration
2016-06-27 21:55:33 +02:00
(segment (start 53.5 19) (end 54.1985 19) (width 0.25) (layer B.Cu) (net 36))
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(segment (start 68.199 27.432) (end 62.21498 21.44798) (width 0.3) (layer F.Cu) (net 37))
(segment (start 62.21498 21.44798) (end 62.21498 20.954521) (width 0.3) (layer F.Cu) (net 37))
(segment (start 68.199 39.624) (end 68.199 27.432) (width 0.3) (layer F.Cu) (net 37))
(segment (start 65.913 41.91) (end 68.199 39.624) (width 0.3) (layer F.Cu) (net 37))
(segment (start 47.625 41.91) (end 65.913 41.91) (width 0.3) (layer F.Cu) (net 37))
(segment (start 62.514979 20.654522) (end 62.21498 20.954521) (width 0.3) (layer B.Cu) (net 37))
(segment (start 63.27 19.899501) (end 62.514979 20.654522) (width 0.3) (layer B.Cu) (net 37))
(segment (start 63.27 18.166) (end 63.27 19.899501) (width 0.3) (layer B.Cu) (net 37))
(via (at 62.21498 20.954521) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 37))
Completed routing iteration
2016-06-27 21:55:33 +02:00
(segment (start 41.91 51.435) (end 41.91 46.214998) (width 0.3) (layer B.Cu) (net 37))
(segment (start 41.91 46.214998) (end 46.214998 41.91) (width 0.3) (layer B.Cu) (net 37))
(segment (start 46.214998 41.91) (end 47.625 41.91) (width 0.3) (layer B.Cu) (net 37))
(via (at 47.625 41.91) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 37))
(segment (start 36.83 65.786) (end 36.83 64.6605) (width 0.3) (layer F.Cu) (net 37))
(via (at 41.91 51.435) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 37))
(segment (start 36.83 64.6605) (end 38.804001 62.686499) (width 0.3) (layer F.Cu) (net 37))
(segment (start 38.804001 62.686499) (end 38.804001 54.540999) (width 0.3) (layer F.Cu) (net 37))
(segment (start 38.804001 54.540999) (end 41.91 51.435) (width 0.3) (layer F.Cu) (net 37))
(segment (start 53.975 48.895) (end 53.975 47.205) (width 0.3) (layer B.Cu) (net 38))
(segment (start 53.975 47.205) (end 53.25 46.48) (width 0.3) (layer B.Cu) (net 38))
(segment (start 53.72328 46.8358) (end 53.72328 48.64328) (width 0.3) (layer F.Cu) (net 38))
(segment (start 53.72328 48.64328) (end 53.975 48.895) (width 0.3) (layer F.Cu) (net 38))
(via (at 53.975 48.895) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 38))
(segment (start 58.5452 52.8302) (end 58.20182 52.48682) (width 0.3) (layer F.Cu) (net 39))
(segment (start 60.5 52.8302) (end 58.5452 52.8302) (width 0.3) (layer F.Cu) (net 39))
(via (at 58.20182 52.48682) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 39))
(segment (start 58.20182 50.28482) (end 58.20182 52.062556) (width 0.3) (layer B.Cu) (net 39))
(segment (start 58.20182 52.062556) (end 58.20182 52.48682) (width 0.3) (layer B.Cu) (net 39))
(segment (start 55.88 47.963) (end 58.20182 50.28482) (width 0.3) (layer B.Cu) (net 39))
(segment (start 55.88 39.665) (end 55.88 47.963) (width 0.3) (layer B.Cu) (net 39))
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(segment (start 34.671 26.289) (end 34.671 24.815144) (width 0.3) (layer B.Cu) (net 40))
(segment (start 34.671 24.815144) (end 34.804466 24.681678) (width 0.3) (layer B.Cu) (net 40))
Completed routing iteration
2016-06-27 21:55:33 +02:00
(segment (start 50.93436 52.83782) (end 49.02782 52.83782) (width 0.3) (layer F.Cu) (net 40))
(segment (start 49.02782 52.83782) (end 48.895 52.705) (width 0.3) (layer F.Cu) (net 40))
(segment (start 48.895 29.21) (end 48.895 52.705) (width 0.25) (layer B.Cu) (net 40))
(via (at 48.895 52.705) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 40))
(segment (start 45.085 25.4) (end 48.895 29.21) (width 0.25) (layer B.Cu) (net 40))
(segment (start 42.545 25.4) (end 45.085 25.4) (width 0.25) (layer B.Cu) (net 40))
(segment (start 37.465 25.4) (end 42.545 25.4) (width 0.25) (layer F.Cu) (net 40))
(via (at 42.545 25.4) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 40))
(segment (start 36.83 26.035) (end 37.465 25.4) (width 0.25) (layer F.Cu) (net 40))
(segment (start 36.879466 24.681678) (end 36.879466 25.985534) (width 0.25) (layer B.Cu) (net 40))
(segment (start 36.879466 25.985534) (end 36.83 26.035) (width 0.25) (layer B.Cu) (net 40))
(via (at 36.83 26.035) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 40))
(segment (start 36.879466 24.681678) (end 34.804466 24.681678) (width 0.25) (layer B.Cu) (net 40))
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(segment (start 45.471725 51.511309) (end 44.532034 52.451) (width 0.3) (layer B.Cu) (net 41))
(segment (start 43.561 55.367) (end 43.561 55.142) (width 0.3) (layer B.Cu) (net 41))
(segment (start 43.561 55.142) (end 44.532034 54.170966) (width 0.3) (layer B.Cu) (net 41))
(segment (start 44.532034 54.170966) (end 44.532034 52.451) (width 0.3) (layer B.Cu) (net 41))
(segment (start 42 55.48) (end 43.448 55.48) (width 0.3) (layer B.Cu) (net 41))
(segment (start 43.448 55.48) (end 43.561 55.367) (width 0.3) (layer B.Cu) (net 41))
Completed routing iteration
2016-06-27 21:55:33 +02:00
(segment (start 42 55.48) (end 39.989442 55.48) (width 0.3) (layer B.Cu) (net 41))
(segment (start 39.989442 55.48) (end 39.924664 55.415222) (width 0.3) (layer B.Cu) (net 41))
(segment (start 42 55.33) (end 42 55.48) (width 0.3) (layer B.Cu) (net 41))
(segment (start 48.26 53.34) (end 48.26 52.915736) (width 0.3) (layer B.Cu) (net 41))
(segment (start 48.26 52.915736) (end 46.855573 51.511309) (width 0.3) (layer B.Cu) (net 41))
(segment (start 46.855573 51.511309) (end 45.471725 51.511309) (width 0.3) (layer B.Cu) (net 41))
(segment (start 50.93436 53.63792) (end 48.55792 53.63792) (width 0.3) (layer F.Cu) (net 41))
(segment (start 48.55792 53.63792) (end 48.26 53.34) (width 0.3) (layer F.Cu) (net 41))
(via (at 48.26 53.34) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 41))
(segment (start 33.075 40.055) (end 33.075 38.495) (width 0.3) (layer B.Cu) (net 42))
(segment (start 33.075 38.495) (end 32.68 38.1) (width 0.3) (layer B.Cu) (net 42))
(segment (start 34.29 40.005) (end 33.125 40.005) (width 0.3) (layer B.Cu) (net 42))
(segment (start 33.125 40.005) (end 33.075 40.055) (width 0.3) (layer B.Cu) (net 42))
(segment (start 50.93436 54.43802) (end 46.197294 54.43802) (width 0.3) (layer F.Cu) (net 42))
(segment (start 46.197294 54.43802) (end 34.29 42.530726) (width 0.3) (layer F.Cu) (net 42))
(segment (start 34.29 42.530726) (end 34.29 40.005) (width 0.3) (layer F.Cu) (net 42))
(via (at 34.29 40.005) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 42))
(segment (start 30.535 41.96) (end 30.662 41.96) (width 0.3) (layer B.Cu) (net 43))
(segment (start 31.266001 39.636001) (end 30.48 38.85) (width 0.3) (layer B.Cu) (net 43))
(segment (start 30.662 41.96) (end 31.266001 41.355999) (width 0.3) (layer B.Cu) (net 43))
(segment (start 31.266001 41.355999) (end 31.266001 39.636001) (width 0.3) (layer B.Cu) (net 43))
(segment (start 30.48 38.85) (end 30.48 38.1) (width 0.3) (layer B.Cu) (net 43))
(segment (start 30.65 43.815) (end 30.65 42.075) (width 0.3) (layer B.Cu) (net 43))
(segment (start 30.65 42.075) (end 30.535 41.96) (width 0.3) (layer B.Cu) (net 43))
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(segment (start 63.515001 51.757999) (end 65.786 49.487) (width 0.3) (layer F.Cu) (net 44))
(segment (start 65.786 49.487) (end 65.786 47.031) (width 0.3) (layer F.Cu) (net 44))
Completed routing iteration
2016-06-27 21:55:33 +02:00
(segment (start 62.254002 53.643) (end 63.515001 52.382001) (width 0.3) (layer F.Cu) (net 44))
(segment (start 63.515001 51.757999) (end 63.530021 51.742979) (width 0.3) (layer F.Cu) (net 44))
(segment (start 63.515001 52.382001) (end 63.515001 51.757999) (width 0.3) (layer F.Cu) (net 44))
(segment (start 60.5 53.643) (end 62.254002 53.643) (width 0.3) (layer F.Cu) (net 44))
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(segment (start 63.881 47.031) (end 63.131 47.031) (width 0.3) (layer F.Cu) (net 48))
(segment (start 63.131 47.031) (end 62.9358 46.8358) (width 0.3) (layer F.Cu) (net 48))
(segment (start 62.9358 46.8358) (end 60.806202 46.8358) (width 0.3) (layer F.Cu) (net 48))
Completed routing iteration
2016-06-27 21:55:33 +02:00
(segment (start 58.52388 46.8358) (end 60.806202 46.8358) (width 0.3) (layer F.Cu) (net 48))
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(segment (start 63.881 44.681) (end 63.881 44.831) (width 0.3) (layer F.Cu) (net 52))
(segment (start 62.865 21.390878) (end 68.699011 27.224889) (width 0.3) (layer F.Cu) (net 52))
(segment (start 68.699011 27.224889) (end 68.699011 39.862989) (width 0.3) (layer F.Cu) (net 52))
(segment (start 62.865 20.447) (end 62.865 21.390878) (width 0.3) (layer F.Cu) (net 52))
(segment (start 61.341 19.812) (end 62.23 19.812) (width 0.3) (layer F.Cu) (net 52))
(segment (start 68.699011 39.862989) (end 63.881 44.681) (width 0.3) (layer F.Cu) (net 52))
(segment (start 62.23 19.812) (end 62.865 20.447) (width 0.3) (layer F.Cu) (net 52))
(segment (start 61.341 19.812) (end 60.73 19.201) (width 0.3) (layer B.Cu) (net 52))
(segment (start 60.73 19.201) (end 60.73 18.166) (width 0.3) (layer B.Cu) (net 52))
(via (at 61.341 19.812) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 52))
(segment (start 60.73 18.166) (end 60.73 18.56605) (width 0.3) (layer B.Cu) (net 52))
(segment (start 63.050696 21.844) (end 63.344044 21.550652) (width 0.3) (layer B.Cu) (net 53))
(segment (start 63.344044 21.550652) (end 63.644043 21.250653) (width 0.3) (layer B.Cu) (net 53))
(segment (start 59.46 18.166) (end 59.46 19.16577) (width 0.3) (layer B.Cu) (net 53))
(segment (start 65.786 43.931) (end 69.199022 40.517978) (width 0.3) (layer F.Cu) (net 53))
(segment (start 65.786 44.831) (end 65.786 43.931) (width 0.3) (layer F.Cu) (net 53))
(segment (start 69.199022 40.517978) (end 69.199022 26.945278) (width 0.3) (layer F.Cu) (net 53))
(segment (start 69.199022 26.945278) (end 63.944042 21.690298) (width 0.3) (layer F.Cu) (net 53))
(segment (start 63.944042 21.690298) (end 63.944042 21.550652) (width 0.3) (layer F.Cu) (net 53))
(segment (start 63.944042 21.550652) (end 63.644043 21.250653) (width 0.3) (layer F.Cu) (net 53))
(via (at 63.644043 21.250653) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 53))
(segment (start 62.13823 21.844) (end 63.050696 21.844) (width 0.3) (layer B.Cu) (net 53))
(segment (start 59.46 19.16577) (end 62.13823 21.844) (width 0.3) (layer B.Cu) (net 53))
(segment (start 59.85505 22.225) (end 57.254 22.225) (width 0.3) (layer B.Cu) (net 54))
(segment (start 57.254 22.225) (end 56.388 21.359) (width 0.3) (layer B.Cu) (net 54))
(segment (start 56.388 21.359) (end 56.388 21.209) (width 0.3) (layer B.Cu) (net 54))
(segment (start 59.85505 22.225) (end 60.73 23.09995) (width 0.25) (layer B.Cu) (net 54))
(segment (start 60.73 23.09995) (end 60.73 23.5) (width 0.25) (layer B.Cu) (net 54))
Completed routing iteration
2016-06-27 21:55:33 +02:00
(zone (net 2) (net_name GND) (layer F.Cu) (tstamp 0) (hatch edge 0.508)
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First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(xy 17.145 16.002) (xy 17.145 72.39) (xy 71.247 72.39) (xy 71.247 15.875)
Completed routing iteration
2016-06-27 21:55:33 +02:00
)
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Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
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Completed routing iteration
2016-06-27 21:55:33 +02:00
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Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
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First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
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(xy 32.315377 51.885119) (xy 32.225829 51.994136) (xy 32.135181 52.102166) (xy 32.131315 52.109198) (xy 32.126215 52.115407)
(xy 32.059541 52.239755) (xy 31.991609 52.363322) (xy 31.989181 52.370976) (xy 31.985387 52.378052) (xy 31.944144 52.512951)
(xy 31.901498 52.64739) (xy 31.900603 52.655367) (xy 31.898255 52.663048) (xy 31.883998 52.803404) (xy 31.868278 52.943551)
(xy 31.868168 52.959241) (xy 31.868138 52.95954) (xy 31.868164 52.959818) (xy 31.868129 52.964871) (xy 31.868129 58.477629)
(xy 31.881898 58.618061) (xy 31.894187 58.758522) (xy 31.896426 58.766229) (xy 31.89721 58.774225) (xy 31.93799 58.909293)
(xy 31.977331 59.044708) (xy 31.981027 59.051838) (xy 31.983347 59.059523) (xy 32.049563 59.184058) (xy 32.114479 59.309293)
(xy 32.119488 59.315568) (xy 32.123258 59.322658) (xy 32.212429 59.431992) (xy 32.300407 59.5422) (xy 32.311425 59.553373)
(xy 32.311614 59.553605) (xy 32.311828 59.553782) (xy 32.315377 59.557381) (xy 32.680447 59.922451) (xy 27.432 59.922451)
(xy 27.348077 59.929143) (xy 27.205735 59.973224) (xy 27.08131 60.055215) (xy 26.984652 60.168624) (xy 26.923416 60.304471)
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
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(xy 19.854255 62.092717) (xy 19.983985 62.420379) (xy 20.174889 62.716603) (xy 20.419693 62.970106) (xy 20.709074 63.171231)
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(xy 23.086265 68.423776) (xy 23.21069 68.341785) (xy 23.307348 68.228376) (xy 23.368584 68.092529) (xy 23.389549 67.945)
(xy 23.389549 65.405) (xy 23.382857 65.321077) (xy 23.338776 65.178735) (xy 23.256785 65.05431) (xy 23.18728 64.995071)
(xy 23.193177 64.996874) (xy 23.333548 65.011133) (xy 23.47368 65.026851) (xy 23.48937 65.026961) (xy 23.489669 65.026991)
(xy 23.489947 65.026965) (xy 23.495 65.027) (xy 26.902451 65.027) (xy 26.902451 66.548) (xy 26.909143 66.631923)
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(xy 26.953224 66.774265) (xy 27.035215 66.89869) (xy 27.113546 66.965451) (xy 26.705 66.965451) (xy 26.621077 66.972143)
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(xy 25.351097 67.379441) (xy 25.347954 67.381112) (xy 25.299503 67.420628) (xy 25.250619 67.459652) (xy 25.245663 67.464539)
(xy 25.245563 67.464621) (xy 25.245486 67.464714) (xy 25.243889 67.466289) (xy 23.220892 69.489286) (xy 23.119619 69.457937)
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Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(xy 19.15065 71.107) (xy 19.0554 71.20225) (xy 19.0554 71.788) (xy 18.128 71.788) (xy 18.128 69.926475)
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(xy 19.0554 69.926475) (xy 19.0554 70.75775) (xy 19.15065 70.853) (xy 20.173 70.853) (xy 20.173 69.67825)
(xy 20.07775 69.583) (xy 19.398875 69.583) (xy 19.325267 69.597642) (xy 19.255929 69.626362) (xy 19.193527 69.668058)
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(xy 19.140458 69.721126) (xy 19.098762 69.783529) (xy 19.070042 69.852866) (xy 19.0554 69.926475) (xy 18.128 69.926475)
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(xy 18.128 50.951097) (xy 18.128 37.614415) (xy 19.175664 37.614415) (xy 19.238573 37.957178) (xy 19.36686 38.281193)
Completed routing iteration
2016-06-27 21:55:33 +02:00
(xy 19.555639 38.57412) (xy 19.797718 38.824801) (xy 20.083879 39.023688) (xy 20.40322 39.163205) (xy 20.743578 39.238037)
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(xy 34.68053 37.265961) (xy 34.675664 37.614415) (xy 22.727556 37.614415) (xy 22.732076 37.290756) (xy 22.664388 36.948905)
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(xy 21.141646 35.689184) (xy 20.793167 35.686751) (xy 20.450852 35.752051) (xy 20.12774 35.882597) (xy 19.836137 36.073416)
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(xy 19.587153 36.31724) (xy 19.390269 36.604782) (xy 19.252985 36.925089) (xy 19.18053 37.265961) (xy 19.175664 37.614415)
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(xy 18.128 37.614415) (xy 18.128 31.244009) (xy 40.26897 31.244009) (xy 40.331879 31.586772) (xy 40.460166 31.910787)
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(xy 40.648945 32.203714) (xy 40.891024 32.454395) (xy 41.177185 32.653282) (xy 41.496526 32.792799) (xy 41.836884 32.867631)
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Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(xy 18.128 31.244009) (xy 18.128 22.86) (xy 19.536451 22.86) (xy 19.536451 25.4) (xy 19.543143 25.483923)
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(xy 23.114584 25.547529) (xy 23.135549 25.4) (xy 23.135549 25.128394) (xy 27.470992 25.128394) (xy 27.525051 25.422935)
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
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Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(xy 27.537435 24.536047) (xy 27.475173 24.828963) (xy 27.470992 25.128394) (xy 23.135549 25.128394) (xy 23.135549 22.86)
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(xy 19.536451 22.86) (xy 18.128 22.86) (xy 18.128 22.158633) (xy 32.775047 22.158633) (xy 32.811766 22.358376)
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
(xy 32.886747 22.547116) (xy 32.900956 22.573698) (xy 33.058499 22.641408) (xy 33.62781 22.072097) (xy 33.98702 22.072097)
(xy 34.556331 22.641408) (xy 34.713874 22.573698) (xy 34.794315 22.387218) (xy 34.836829 22.188629) (xy 34.839783 21.985561)
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(xy 33.62781 22.072097) (xy 33.058499 21.502786) (xy 32.900956 21.570496) (xy 32.820515 21.756976) (xy 32.778001 21.955565)
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(xy 32.775047 22.158633) (xy 18.128 22.158633) (xy 18.128 21.323181) (xy 33.238104 21.323181) (xy 33.807415 21.892492)
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
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Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
(xy 18.128 21.323181) (xy 18.128 20.241879) (xy 20.323726 20.241879) (xy 20.466478 20.46286) (xy 20.758821 20.605348)
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(xy 20.323726 17.858121) (xy 18.128 17.858121) (xy 18.128 16.604) (xy 27.680604 16.604)
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
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(xy 46.240411 66.902084) (xy 48.096451 65.046045)
Completed routing iteration
2016-06-27 21:55:33 +02:00
)
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Added C for current meas. opamp
2016-06-29 23:00:58 +02:00
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Completed routing iteration
2016-06-27 21:55:33 +02:00
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First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
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Completed routing iteration
2016-06-27 21:55:33 +02:00
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First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
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Completed routing iteration
2016-06-27 21:55:33 +02:00
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First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
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Completed routing iteration
2016-06-27 21:55:33 +02:00
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Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
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Completed routing iteration
2016-06-27 21:55:33 +02:00
)
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First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
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Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
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First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
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Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
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First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
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Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
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(xy 67.324642 52.466867) (xy 67.31 52.540475) (xy 66.054604 52.540475) (xy 66.051018 52.528601) (xy 66.033585 52.468594)
First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
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Completed routing iteration
2016-06-27 21:55:33 +02:00
)
)
Finished layout (still needs review)
2016-09-08 22:27:29 +02:00
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Completed routing iteration
2016-06-27 21:55:33 +02:00
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First iteration towards v1.1 - Added EMI-blocking capacitors at all power inputs and outputs - Added protection resistors on FET driver inputs - Added gate resistor - Replaced 3.3V-LDO with more power saving version - Inverted logical pin ordering on UART port (physical ordering is unchanged) - Added first bunch of mounting holes - Adapted layout
2016-09-07 22:48:31 +02:00
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Completed routing iteration
2016-06-27 21:55:33 +02:00
)
)
)
Initial commit - Full schematic - Partially placed board
2016-06-26 00:26:23 +02:00
)
Reference in a new issue Copy permalink