2016-07-28 02:14:03 +02:00
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#include <libopencm3/stm32/rcc.h>
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#include <libopencm3/stm32/adc.h>
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#include <libopencm3/stm32/gpio.h>
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#include <libopencm3/stm32/dma.h>
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#include <libopencm3/stm32/timer.h>
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#include <libopencm3/cm3/nvic.h>
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#include <libopencm3/cm3/systick.h>
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2016-08-07 01:04:24 +02:00
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#include <libopencmsis/core_cm3.h>
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2016-07-28 02:14:03 +02:00
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#include <fxp.h>
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#include <fxp_basic.h>
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2016-08-05 00:06:11 +02:00
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#include "lcd.h"
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2016-07-28 02:14:03 +02:00
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#include "debug.h"
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2016-08-06 03:13:41 +02:00
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#define CONV_PWM_PERIOD 960
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#define CONV_PWM_MAX (98*CONV_PWM_PERIOD/100)
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2016-08-05 20:48:36 +02:00
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#define TIM_CH_CONV TIM_OC1
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#define TIM_CH_BOOTSTRAP TIM_OC2
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2016-08-06 01:27:11 +02:00
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enum OperState {
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Bootstrap,
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2016-08-06 03:13:41 +02:00
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ConvConstVoltage,
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2016-08-06 22:22:21 +02:00
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ConvConstCurrent,
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2016-08-07 00:36:15 +02:00
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ConvMPP,
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2016-08-06 01:27:11 +02:00
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Idle,
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};
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2016-07-28 02:14:03 +02:00
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volatile int wait_frame = 1;
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#define ADC_NUM_CHANNELS 3
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volatile uint16_t adc_values[ADC_NUM_CHANNELS];
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static void init_gpio(void)
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{
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// Set up UART TX on PB6 for debugging
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gpio_mode_setup(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO6);
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gpio_set_af(GPIOB, GPIO_AF0, GPIO6);
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2016-08-05 00:27:40 +02:00
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// GPIO for converter switch
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2016-08-06 01:27:11 +02:00
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gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO8);
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gpio_set_af(GPIOA, GPIO_AF2, GPIO8);
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2016-08-05 00:27:40 +02:00
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// GPIO for bootstrap pulse
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2016-08-06 01:27:11 +02:00
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gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO9);
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gpio_set_af(GPIOA, GPIO_AF2, GPIO9);
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2016-08-05 00:27:40 +02:00
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// GPIO for load activation
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gpio_mode_setup(GPIOA, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO15);
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gpio_set(GPIOA, GPIO15);
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2016-07-28 02:14:03 +02:00
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}
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static void init_clock(void)
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{
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/* Set STM32 to 48 MHz. */
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// Relevant for Timers
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//rcc_clock_setup_in_hse_8mhz_out_48mhz();
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rcc_clock_setup_in_hsi_out_48mhz();
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// enable GPIO clocks:
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2016-08-05 00:06:11 +02:00
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// Port A is needed for the Display and more
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2016-07-28 02:14:03 +02:00
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rcc_periph_clock_enable(RCC_GPIOA);
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2016-08-05 00:06:11 +02:00
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// Port B is needed for debugging
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2016-07-28 02:14:03 +02:00
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rcc_periph_clock_enable(RCC_GPIOB);
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// enable TIM3 for scheduling
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rcc_periph_clock_enable(RCC_TIM3);
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2016-08-05 20:48:36 +02:00
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// enable TIM1 for PWM generation
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rcc_periph_clock_enable(RCC_TIM1);
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2016-07-28 02:14:03 +02:00
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// enable ADC1 clock
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rcc_periph_clock_enable(RCC_ADC1);
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// enable DMA
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rcc_periph_clock_enable(RCC_DMA);
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}
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static void init_timer(void)
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{
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// *** TIM1 ***
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2016-08-05 20:48:36 +02:00
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// Configure channels 1 and 2 for PWM (-> Pins PA8, PA9)
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// Ch1 = Buck converter switch, Ch2 = bootstrap pulse
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timer_reset(TIM1);
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2016-07-28 02:14:03 +02:00
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2016-08-05 20:48:36 +02:00
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timer_set_mode(TIM1, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
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2016-07-28 02:14:03 +02:00
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2016-08-05 20:48:36 +02:00
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// set up PWM channels
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timer_set_oc_mode(TIM1, TIM_CH_CONV, TIM_OCM_PWM1);
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timer_enable_oc_output(TIM1, TIM_CH_CONV);
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timer_enable_oc_preload(TIM1, TIM_CH_CONV);
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timer_set_oc_polarity_high(TIM1, TIM_CH_CONV);
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2016-07-28 02:14:03 +02:00
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2016-08-05 20:48:36 +02:00
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timer_set_oc_mode(TIM1, TIM_CH_BOOTSTRAP, TIM_OCM_PWM1);
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timer_enable_oc_output(TIM1, TIM_CH_BOOTSTRAP);
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timer_enable_oc_preload(TIM1, TIM_CH_BOOTSTRAP);
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2016-08-06 01:27:11 +02:00
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timer_set_oc_polarity_high(TIM1, TIM_CH_BOOTSTRAP);
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2016-07-28 02:14:03 +02:00
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2016-08-05 20:48:36 +02:00
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timer_set_oc_value(TIM1, TIM_CH_CONV, 0); // no PWM by default
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timer_set_oc_value(TIM1, TIM_CH_BOOTSTRAP, 0); // no PWM by default
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2016-07-28 02:14:03 +02:00
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2016-08-05 20:48:36 +02:00
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// wanted: 50 kHz / 20 us period
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// system clock: 48 MHz
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2016-08-06 03:13:41 +02:00
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// => 960 clock cycles / period = CONV_PWM_PERIOD
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2016-07-28 02:14:03 +02:00
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// prescaler
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2016-08-05 20:48:36 +02:00
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timer_set_prescaler(TIM1, 0); // Timer runs at system clock
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2016-07-28 02:14:03 +02:00
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// auto-reload value
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2016-08-06 03:13:41 +02:00
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timer_set_period(TIM1, CONV_PWM_PERIOD - 1);
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2016-07-28 02:14:03 +02:00
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2016-08-06 01:27:11 +02:00
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// only generate interrupt on overflow
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timer_update_on_overflow(TIM1);
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// enable master output bit
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timer_enable_break_main_output(TIM1);
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2016-07-28 02:14:03 +02:00
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// *** TIM3 ***
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// used for the 1-millisecond system tick
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timer_reset(TIM3);
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timer_set_mode(TIM3, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
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// prescaler
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timer_set_prescaler(TIM3, 47); // -> 1 us counting at 48 MHz
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// auto-reload value
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timer_set_period(TIM3, 999); // -> update interrupt every 1 ms
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// enable update interrupt (triggered on timer restart)
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timer_enable_irq(TIM3, TIM_DIER_UIE);
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nvic_enable_irq(NVIC_TIM3_IRQ);
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2016-08-05 20:48:54 +02:00
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// Start all the timers!
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2016-07-28 02:14:03 +02:00
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timer_enable_counter(TIM3);
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2016-08-05 20:48:54 +02:00
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timer_enable_counter(TIM1);
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2016-07-28 02:14:03 +02:00
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}
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static void init_adc(void)
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{
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uint8_t channels[ADC_NUM_CHANNELS] = {
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ADC_CHANNEL0, // VInSense
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ADC_CHANNEL1, // VOutSense
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ADC_CHANNEL2 // CurrentSense
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};
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adc_power_off(ADC1);
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// configure ADC
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//adc_enable_scan_mode(ADC1);
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adc_set_single_conversion_mode(ADC1);
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adc_set_resolution(ADC1, ADC_RESOLUTION_12BIT);
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adc_set_sample_time_on_all_channels(ADC1, ADC_SMPR_SMP_071DOT5);
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adc_disable_external_trigger_regular(ADC1);
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adc_set_right_aligned(ADC1);
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adc_set_regular_sequence(ADC1, ADC_NUM_CHANNELS, channels);
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// configure DMA for ADC
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//nvic_enable_irq(NVIC_DMA1_STREAM5_IRQ);
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dma_channel_reset(DMA1, DMA_CHANNEL1);
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dma_set_priority(DMA1, DMA_CHANNEL1, DMA_CCR_PL_LOW);
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dma_set_memory_size(DMA1, DMA_CHANNEL1, DMA_CCR_MSIZE_16BIT);
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dma_set_peripheral_size(DMA1, DMA_CHANNEL1, DMA_CCR_PSIZE_16BIT);
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dma_enable_memory_increment_mode(DMA1, DMA_CHANNEL1);
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dma_enable_circular_mode(DMA1, DMA_CHANNEL1);
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dma_set_read_from_peripheral(DMA1, DMA_CHANNEL1);
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dma_set_peripheral_address(DMA1, DMA_CHANNEL1, (uint32_t) &ADC1_DR);
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2016-08-05 20:48:54 +02:00
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/* The array adc_values[] is filled with the waveform data to be output */
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2016-07-28 02:14:03 +02:00
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dma_set_memory_address(DMA1, DMA_CHANNEL1, (uint32_t) adc_values);
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dma_set_number_of_data(DMA1, DMA_CHANNEL1, ADC_NUM_CHANNELS);
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//dma_enable_transfer_complete_interrupt(DMA1, DMA_CHANNEL1);
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dma_enable_channel(DMA1, DMA_CHANNEL1);
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adc_enable_dma(ADC1);
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// GO!
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adc_power_on(ADC1);
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}
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#if 0
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/* Set up timer to fire freq times per second */
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static void init_systick(int freq)
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{
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systick_set_clocksource(STK_CSR_CLKSOURCE_AHB);
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/* clear counter so it starts right away */
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STK_CVR = 0;
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systick_set_reload(rcc_ahb_frequency / freq);
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systick_counter_enable();
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systick_interrupt_enable();
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}
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#endif
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int main(void)
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{
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uint16_t cpuload = 0;
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uint64_t timebase_ms = 0;
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2016-08-06 01:27:11 +02:00
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uint32_t time_in_state = 0;
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2016-07-28 02:14:03 +02:00
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char msg[128];
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char number[FXP_STR_MAXLEN];
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uint8_t sentSomething = 0;
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2016-08-13 01:12:33 +02:00
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int32_t pwm = 0;
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2016-08-06 22:22:21 +02:00
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2016-08-06 01:27:11 +02:00
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enum OperState operState = Bootstrap;
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2016-08-06 22:22:21 +02:00
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enum OperState nextState = ConvConstVoltage;
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2016-08-06 01:27:11 +02:00
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enum OperState lastState = operState;
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fxp_t vin, vout, current;
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2016-08-06 22:22:21 +02:00
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fxp_t vin_avg = 0, vout_avg = 0, current_avg = 0;
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2016-08-06 01:27:11 +02:00
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2016-08-13 01:12:33 +02:00
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fxp_t pErr = 0, iErr = 0;
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fxp_t controlAction = 0;
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2016-08-06 03:13:41 +02:00
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2016-08-13 01:12:33 +02:00
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fxp_t power_avg, refPower = 0;
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2016-08-07 00:36:15 +02:00
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fxp_t testPower[2];
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int32_t testPWM[2];
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2016-08-13 01:12:33 +02:00
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int testPWMStep = 5;
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2016-08-07 00:36:15 +02:00
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2016-08-06 22:22:21 +02:00
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fxp_t PGAIN_CV = fxp_from_float( 50.000f);
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fxp_t IGAIN_CV = fxp_from_float( 0.300f);
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fxp_t IERR_LIMIT = fxp_from_int(4000);
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fxp_t PGAIN_CC = fxp_from_float( 50.000f);
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fxp_t IGAIN_CC = fxp_from_float( 0.300f);
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2016-08-06 03:13:41 +02:00
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2016-08-13 01:12:33 +02:00
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fxp_t CURRENT_THRESHOLD = fxp_from_float(0.01f);
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2016-08-06 03:13:41 +02:00
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2016-08-06 22:22:21 +02:00
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fxp_t AVG_FACT = fxp_from_float(0.10f);
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fxp_t AVG_FACT_INV = fxp_sub(fxp_from_int(1), AVG_FACT);
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2016-08-13 01:12:33 +02:00
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fxp_t MAX_VOLTAGE = fxp_from_float(14.400f);
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fxp_t CONST_VOLTAGE = fxp_from_float(13.800f);
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2016-08-07 00:36:15 +02:00
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fxp_t MAX_CURRENT = fxp_from_float( 5.000f);
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2016-08-13 01:12:33 +02:00
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fxp_t MPP_VOLTAGE_THR = fxp_sub(CONST_VOLTAGE, fxp_from_float(0.500f));
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2016-08-07 00:36:15 +02:00
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fxp_t MPP_CURRENT_THR = fxp_sub(MAX_CURRENT, fxp_from_float(0.500f));
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2016-08-06 03:13:41 +02:00
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2016-08-04 23:17:25 +02:00
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// Calculated values
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2016-07-28 02:14:03 +02:00
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//fxp_t VIN_SCALE = fxp_from_float(3.3f * (100 + 12.4f) / 12.4f / 4095.0f);
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//fxp_t VOUT_SCALE = fxp_from_float(3.3f * (100 + 12.0f) / 12.0f / 4095.0f);
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2016-08-04 23:17:25 +02:00
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//fxp_t CURRENT_SCALE = fxp_from_float(9.7f / 4095.0f);
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// Calibrated from measurements
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2016-07-28 02:14:03 +02:00
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fxp_t VIN_SCALE = fxp_from_float(12.11f / 1600.0f);
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fxp_t VOUT_SCALE = fxp_from_float(12.6f / 1620.0f);
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2016-08-04 23:17:25 +02:00
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fxp_t CURRENT_SCALE = fxp_from_float(9.01f / 4095.0f);
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2016-07-28 02:14:03 +02:00
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2016-08-06 22:22:21 +02:00
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fxp_t CURRENT_OFFSET = fxp_from_float(0.049);
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2016-07-28 02:14:03 +02:00
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init_clock();
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init_gpio();
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init_adc();
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init_timer();
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lcd_init();
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debug_init();
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debug_send_string("Init complete\r\n");
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//init_systick(1000);
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// triggered every 1 ms
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while (1) {
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// let the ADC+DMA do its work
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adc_start_conversion_regular(ADC1);
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2016-08-06 01:27:11 +02:00
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// *** Do some calculations while ADC converts ***
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2016-07-28 02:14:03 +02:00
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2016-08-05 00:06:11 +02:00
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if(lcd_setup()) {
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2016-07-28 02:14:03 +02:00
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lcd_process();
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if((timebase_ms % 500) == 0) {
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fxp_t scaled_val;
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lcd_set_cursor_pos(1, 0);
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2016-08-06 22:22:21 +02:00
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fxp_format(vin_avg, number, 1);
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2016-07-28 02:14:03 +02:00
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fxp_right_align(number, msg, 4, ' ');
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lcd_send_string("I:");
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lcd_send_string(msg);
|
|
|
|
lcd_send_string("V ");
|
|
|
|
|
2016-08-06 22:22:21 +02:00
|
|
|
fxp_format(vout_avg, number, 1);
|
2016-07-28 02:14:03 +02:00
|
|
|
fxp_right_align(number, msg, 4, ' ');
|
|
|
|
lcd_send_string("O:");
|
|
|
|
lcd_send_string(msg);
|
|
|
|
lcd_send_string("V ");
|
|
|
|
|
2016-08-06 03:13:41 +02:00
|
|
|
lcd_set_cursor_pos(0, 10);
|
2016-07-28 02:14:03 +02:00
|
|
|
|
2016-08-06 22:22:21 +02:00
|
|
|
scaled_val = fxp_mult(current_avg, fxp_from_int(1000)); // A -> mA
|
2016-07-28 02:14:03 +02:00
|
|
|
fxp_format(scaled_val, number, 0);
|
|
|
|
fxp_right_align(number, msg, 4, ' ');
|
|
|
|
lcd_send_string(msg);
|
|
|
|
lcd_send_string("mA");
|
|
|
|
}
|
|
|
|
|
|
|
|
if((timebase_ms % 1000) == 10) {
|
|
|
|
cpuload /= 1000;
|
|
|
|
|
2016-08-05 00:06:11 +02:00
|
|
|
lcd_set_cursor_pos(0, 0);
|
2016-07-28 02:14:03 +02:00
|
|
|
|
|
|
|
fxp_format_int((int32_t)cpuload, number);
|
|
|
|
fxp_right_align(number, msg, 3, '0');
|
2016-08-06 03:13:41 +02:00
|
|
|
lcd_send_string("L:");
|
2016-07-28 02:14:03 +02:00
|
|
|
lcd_send_string(msg);
|
2016-08-07 16:02:51 +02:00
|
|
|
|
|
|
|
cpuload = 0;
|
2016-07-28 02:14:03 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-08-06 01:27:11 +02:00
|
|
|
|
|
|
|
// wait for DMA transfer to complete
|
|
|
|
while(!dma_get_interrupt_flag(DMA1, DMA_CHANNEL1, DMA_TCIF) && wait_frame);
|
|
|
|
dma_clear_interrupt_flags(DMA1, DMA_CHANNEL1, DMA_TCIF);
|
|
|
|
|
|
|
|
// convert read values
|
|
|
|
vin = fxp_mult(fxp_from_int(adc_values[0]), VIN_SCALE);
|
|
|
|
vout = fxp_mult(fxp_from_int(adc_values[1]), VOUT_SCALE);
|
|
|
|
current = fxp_mult(fxp_from_int(adc_values[2]), CURRENT_SCALE);
|
2016-08-06 22:22:21 +02:00
|
|
|
current = fxp_sub(current, CURRENT_OFFSET);
|
|
|
|
|
|
|
|
vin_avg = fxp_add(fxp_mult(vin, AVG_FACT), fxp_mult(vin_avg, AVG_FACT_INV));
|
|
|
|
vout_avg = fxp_add(fxp_mult(vout, AVG_FACT), fxp_mult(vout_avg, AVG_FACT_INV));
|
|
|
|
current_avg = fxp_add(fxp_mult(current, AVG_FACT), fxp_mult(current_avg, AVG_FACT_INV));
|
2016-08-06 01:27:11 +02:00
|
|
|
|
2016-08-07 00:36:15 +02:00
|
|
|
power_avg = fxp_mult(vout_avg, current_avg);
|
|
|
|
|
2016-08-06 01:27:11 +02:00
|
|
|
// Main FSM
|
|
|
|
if(timebase_ms >= 1000) {
|
|
|
|
switch(operState) {
|
|
|
|
case Bootstrap:
|
2016-08-06 03:13:41 +02:00
|
|
|
// enable bootstrap pulse with very low duty cycle
|
2016-08-06 01:27:11 +02:00
|
|
|
// disable converter
|
|
|
|
timer_set_oc_value(TIM1, TIM_CH_BOOTSTRAP, 48);
|
|
|
|
timer_set_oc_value(TIM1, TIM_CH_CONV, 0);
|
|
|
|
|
2016-08-06 03:13:41 +02:00
|
|
|
if(time_in_state >= 5) { // bootstrap duration in ms
|
2016-08-07 01:04:24 +02:00
|
|
|
iErr = fxp_div(IERR_LIMIT, fxp_from_int(2));
|
2016-08-06 22:22:21 +02:00
|
|
|
operState = nextState;
|
2016-08-06 01:27:11 +02:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
2016-08-06 03:13:41 +02:00
|
|
|
case ConvConstVoltage:
|
|
|
|
// bootstrap off
|
2016-08-06 01:27:11 +02:00
|
|
|
timer_set_oc_value(TIM1, TIM_CH_BOOTSTRAP, 0);
|
2016-08-06 03:13:41 +02:00
|
|
|
|
|
|
|
// calculate error values
|
2016-08-13 01:12:33 +02:00
|
|
|
pErr = fxp_sub(CONST_VOLTAGE, vout_avg);
|
2016-08-06 03:13:41 +02:00
|
|
|
iErr = fxp_add(iErr, pErr);
|
|
|
|
|
|
|
|
// limit integral error range
|
|
|
|
if (iErr > IERR_LIMIT) iErr = IERR_LIMIT;
|
|
|
|
else if(iErr < -IERR_LIMIT) iErr = -IERR_LIMIT;
|
|
|
|
|
|
|
|
// calculate the controller output ("action")
|
|
|
|
controlAction = fxp_add(
|
2016-08-06 22:22:21 +02:00
|
|
|
fxp_mult(pErr, PGAIN_CV),
|
|
|
|
fxp_mult(iErr, IGAIN_CV));
|
|
|
|
|
|
|
|
pwm = fxp_to_int(controlAction);
|
2016-08-06 03:13:41 +02:00
|
|
|
|
2016-08-06 22:22:21 +02:00
|
|
|
if(pwm >= CONV_PWM_MAX) {
|
|
|
|
timer_set_oc_value(TIM1, TIM_CH_CONV, CONV_PWM_MAX);
|
|
|
|
} else if(pwm > 0) {
|
|
|
|
timer_set_oc_value(TIM1, TIM_CH_CONV, pwm);
|
|
|
|
} else {
|
|
|
|
timer_set_oc_value(TIM1, TIM_CH_CONV, 0);
|
|
|
|
}
|
2016-08-06 03:13:41 +02:00
|
|
|
|
2016-08-13 01:12:33 +02:00
|
|
|
if(time_in_state > 5000 && pwm > CONV_PWM_MAX && current < CURRENT_THRESHOLD) {
|
2016-08-06 03:13:41 +02:00
|
|
|
operState = Bootstrap;
|
2016-08-06 22:22:21 +02:00
|
|
|
nextState = ConvConstVoltage;
|
2016-08-06 03:13:41 +02:00
|
|
|
}
|
|
|
|
|
2016-08-07 00:36:15 +02:00
|
|
|
if(time_in_state > 1000 && vout_avg < MPP_VOLTAGE_THR) {
|
|
|
|
operState = ConvMPP;
|
|
|
|
}
|
|
|
|
|
|
|
|
if(current_avg > MAX_CURRENT) {
|
2016-08-06 22:22:21 +02:00
|
|
|
operState = ConvConstCurrent;
|
|
|
|
}
|
2016-08-07 01:04:24 +02:00
|
|
|
|
|
|
|
if(vin_avg < vout_avg) {
|
|
|
|
operState = Idle;
|
|
|
|
}
|
2016-08-06 22:22:21 +02:00
|
|
|
break;
|
|
|
|
|
|
|
|
case ConvConstCurrent:
|
|
|
|
// bootstrap off
|
|
|
|
timer_set_oc_value(TIM1, TIM_CH_BOOTSTRAP, 0);
|
|
|
|
|
|
|
|
// calculate error values
|
2016-08-07 00:36:15 +02:00
|
|
|
pErr = fxp_sub(MAX_CURRENT, current_avg);
|
2016-08-06 22:22:21 +02:00
|
|
|
iErr = fxp_add(iErr, pErr);
|
|
|
|
|
|
|
|
// limit integral error range
|
|
|
|
if (iErr > IERR_LIMIT) iErr = IERR_LIMIT;
|
|
|
|
else if(iErr < -IERR_LIMIT) iErr = -IERR_LIMIT;
|
|
|
|
|
|
|
|
// calculate the controller output ("action")
|
|
|
|
controlAction = fxp_add(
|
|
|
|
fxp_mult(pErr, PGAIN_CC),
|
|
|
|
fxp_mult(iErr, IGAIN_CC));
|
|
|
|
|
|
|
|
pwm = fxp_to_int(controlAction);
|
|
|
|
|
2016-08-06 03:13:41 +02:00
|
|
|
if(pwm >= CONV_PWM_MAX) {
|
|
|
|
timer_set_oc_value(TIM1, TIM_CH_CONV, CONV_PWM_MAX);
|
|
|
|
} else if(pwm > 0) {
|
|
|
|
timer_set_oc_value(TIM1, TIM_CH_CONV, pwm);
|
|
|
|
} else {
|
|
|
|
timer_set_oc_value(TIM1, TIM_CH_CONV, 0);
|
|
|
|
}
|
2016-08-06 22:22:21 +02:00
|
|
|
|
2016-08-13 01:12:33 +02:00
|
|
|
if(time_in_state > 5000 && pwm > CONV_PWM_MAX && current < CURRENT_THRESHOLD) {
|
2016-08-06 22:22:21 +02:00
|
|
|
operState = Bootstrap;
|
|
|
|
nextState = ConvConstCurrent;
|
|
|
|
}
|
|
|
|
|
2016-08-07 00:36:15 +02:00
|
|
|
if(time_in_state > 1000 && current_avg < MPP_CURRENT_THR) {
|
|
|
|
operState = ConvMPP;
|
|
|
|
}
|
|
|
|
|
|
|
|
if(vout_avg > MAX_VOLTAGE) {
|
2016-08-06 22:22:21 +02:00
|
|
|
operState = ConvConstVoltage;
|
|
|
|
}
|
2016-08-06 01:27:11 +02:00
|
|
|
break;
|
|
|
|
|
2016-08-07 00:36:15 +02:00
|
|
|
case ConvMPP:
|
|
|
|
// bootstrap off
|
|
|
|
timer_set_oc_value(TIM1, TIM_CH_BOOTSTRAP, 0);
|
|
|
|
|
|
|
|
if((time_in_state % 50) == 0) {
|
|
|
|
switch(testPWMStep) {
|
|
|
|
case 0:
|
|
|
|
case 2:
|
|
|
|
pwm = testPWM[testPWMStep/2];
|
|
|
|
timer_set_oc_value(TIM1, TIM_CH_CONV, pwm);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 1:
|
|
|
|
case 3:
|
|
|
|
testPower[testPWMStep/2] = power_avg;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 4:
|
|
|
|
if(testPower[1] > testPower[0]) {
|
|
|
|
refPower = testPower[1];
|
|
|
|
pwm = testPWM[1];
|
|
|
|
} else {
|
|
|
|
refPower = testPower[0];
|
|
|
|
pwm = testPWM[0];
|
|
|
|
}
|
|
|
|
|
|
|
|
if(pwm < (CONV_PWM_PERIOD/2) || pwm > CONV_PWM_MAX) {
|
|
|
|
pwm = 3 * CONV_PWM_PERIOD / 4;
|
|
|
|
}
|
|
|
|
|
|
|
|
timer_set_oc_value(TIM1, TIM_CH_CONV, pwm);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 5:
|
|
|
|
// power test is currently idle, but power has changed
|
|
|
|
// too much.
|
|
|
|
// -> start a new one.
|
2016-08-13 01:12:33 +02:00
|
|
|
testPWM[0] = pwm + 4;
|
|
|
|
testPWM[1] = pwm - 3;
|
2016-08-07 00:36:15 +02:00
|
|
|
testPWMStep = 0;
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
testPWMStep = 4;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
testPWMStep++;
|
|
|
|
}
|
|
|
|
|
2016-08-13 01:12:33 +02:00
|
|
|
if(time_in_state > 5000 && current < CURRENT_THRESHOLD) {
|
2016-08-07 00:36:15 +02:00
|
|
|
operState = Bootstrap;
|
|
|
|
nextState = ConvMPP;
|
|
|
|
}
|
|
|
|
|
|
|
|
if(vout_avg > MAX_VOLTAGE) {
|
|
|
|
operState = ConvConstVoltage;
|
|
|
|
}
|
|
|
|
|
|
|
|
if(current_avg > MAX_CURRENT) {
|
|
|
|
operState = ConvConstCurrent;
|
|
|
|
}
|
|
|
|
|
2016-08-07 01:04:24 +02:00
|
|
|
if(vin_avg < vout_avg) {
|
|
|
|
operState = Idle;
|
|
|
|
}
|
|
|
|
|
2016-08-07 00:36:15 +02:00
|
|
|
break;
|
|
|
|
|
2016-08-06 01:27:11 +02:00
|
|
|
case Idle:
|
|
|
|
// disable all PWMs
|
|
|
|
timer_set_oc_value(TIM1, TIM_CH_CONV, 0);
|
|
|
|
timer_set_oc_value(TIM1, TIM_CH_BOOTSTRAP, 0);
|
2016-08-07 01:04:24 +02:00
|
|
|
|
2016-08-13 01:12:33 +02:00
|
|
|
if(time_in_state > 1000 && vin_avg > vout_avg) {
|
2016-08-07 01:04:24 +02:00
|
|
|
operState = Bootstrap;
|
|
|
|
nextState = ConvMPP;
|
|
|
|
}
|
|
|
|
|
2016-08-06 01:27:11 +02:00
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
debug_send_string("Invalid state detected!");
|
|
|
|
sentSomething = 1;
|
|
|
|
|
|
|
|
operState = Idle;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if(operState != lastState) {
|
|
|
|
time_in_state = 0;
|
|
|
|
lastState = operState;
|
2016-08-06 22:22:21 +02:00
|
|
|
|
2016-08-07 00:36:15 +02:00
|
|
|
lcd_set_cursor_pos(0, 6);
|
2016-08-06 22:22:21 +02:00
|
|
|
switch(operState) {
|
|
|
|
case Idle:
|
2016-08-07 00:36:15 +02:00
|
|
|
lcd_send_string("IDL");
|
2016-08-06 22:22:21 +02:00
|
|
|
break;
|
|
|
|
case Bootstrap:
|
2016-08-07 00:36:15 +02:00
|
|
|
lcd_send_string("BTS");
|
2016-08-06 22:22:21 +02:00
|
|
|
break;
|
|
|
|
case ConvConstCurrent:
|
2016-08-07 00:36:15 +02:00
|
|
|
lcd_send_string("CC ");
|
2016-08-06 22:22:21 +02:00
|
|
|
break;
|
|
|
|
case ConvConstVoltage:
|
2016-08-07 00:36:15 +02:00
|
|
|
lcd_send_string("CV ");
|
|
|
|
break;
|
|
|
|
case ConvMPP:
|
|
|
|
lcd_send_string("MPP");
|
2016-08-06 22:22:21 +02:00
|
|
|
break;
|
|
|
|
default:
|
2016-08-07 00:36:15 +02:00
|
|
|
lcd_send_string("???");
|
2016-08-06 22:22:21 +02:00
|
|
|
break;
|
|
|
|
}
|
2016-08-06 01:27:11 +02:00
|
|
|
} else {
|
|
|
|
time_in_state++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if((timebase_ms % 500) == 0) {
|
|
|
|
debug_send_string("ADC:");
|
|
|
|
|
|
|
|
for(uint8_t i = 0; i < ADC_NUM_CHANNELS; i++) {
|
|
|
|
fxp_format_int(adc_values[i], msg);
|
|
|
|
debug_send_string(" ");
|
|
|
|
debug_send_string(msg);
|
|
|
|
}
|
|
|
|
|
|
|
|
sentSomething = 1;
|
|
|
|
}
|
|
|
|
|
2016-08-06 03:13:41 +02:00
|
|
|
if((timebase_ms % 500) == 100) {
|
|
|
|
debug_send_string("pErr=");
|
|
|
|
fxp_format(pErr, msg, 3);
|
|
|
|
debug_send_string(msg);
|
|
|
|
|
|
|
|
debug_send_string("; iErr=");
|
|
|
|
fxp_format(iErr, msg, 3);
|
|
|
|
debug_send_string(msg);
|
|
|
|
|
|
|
|
debug_send_string("; action=");
|
|
|
|
fxp_format(controlAction, msg, 1);
|
|
|
|
debug_send_string(msg);
|
|
|
|
|
|
|
|
sentSomething = 1;
|
|
|
|
}
|
|
|
|
|
2016-08-07 00:36:15 +02:00
|
|
|
if((timebase_ms % 500) == 200) {
|
|
|
|
debug_send_string("power_avg=");
|
|
|
|
fxp_format(power_avg, msg, 2);
|
|
|
|
debug_send_string(msg);
|
|
|
|
|
|
|
|
debug_send_string("; ref=");
|
|
|
|
fxp_format(refPower, msg, 2);
|
|
|
|
debug_send_string(msg);
|
|
|
|
|
|
|
|
debug_send_string("; pwm=");
|
|
|
|
fxp_format_int(pwm, msg);
|
|
|
|
debug_send_string(msg);
|
|
|
|
|
|
|
|
sentSomething = 1;
|
|
|
|
}
|
|
|
|
|
2016-08-06 01:27:11 +02:00
|
|
|
if(sentSomething) {
|
|
|
|
debug_send_string("\r\n");
|
|
|
|
sentSomething = 0;
|
|
|
|
}
|
|
|
|
|
2016-07-28 02:14:03 +02:00
|
|
|
// cpu load = timer1 value after main loop operations
|
|
|
|
cpuload += timer_get_counter(TIM3);
|
|
|
|
|
|
|
|
timebase_ms++;
|
|
|
|
|
2016-08-07 01:04:24 +02:00
|
|
|
while(wait_frame) {
|
|
|
|
__WFI();
|
|
|
|
}
|
|
|
|
|
2016-07-28 02:14:03 +02:00
|
|
|
wait_frame = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Called when systick fires */
|
|
|
|
void sys_tick_handler(void)
|
|
|
|
{
|
|
|
|
wait_frame = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void tim3_isr(void)
|
|
|
|
{
|
|
|
|
// check for update interrupt
|
|
|
|
if(timer_interrupt_source(TIM3, TIM_SR_UIF)) {
|
|
|
|
wait_frame = 0;
|
|
|
|
timer_clear_flag(TIM3, TIM_SR_UIF);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void hard_fault_handler(void)
|
|
|
|
{
|
|
|
|
while (1);
|
|
|
|
}
|