|
|
|
@ -122,45 +122,14 @@ static void init_timer(void)
|
|
|
|
|
timer_enable_irq(TIM3, TIM_DIER_UIE);
|
|
|
|
|
nvic_enable_irq(NVIC_TIM3_IRQ);
|
|
|
|
|
|
|
|
|
|
// GO!
|
|
|
|
|
// Start all the timers!
|
|
|
|
|
timer_enable_counter(TIM3);
|
|
|
|
|
timer_enable_counter(TIM1);
|
|
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void init_adc(void)
|
|
|
|
|
{
|
|
|
|
|
#if 0
|
|
|
|
|
//adc_set_multi_mode(ADC_CCR_MULTI_INDEPENDENT);
|
|
|
|
|
|
|
|
|
|
adc_off(ADC2);
|
|
|
|
|
|
|
|
|
|
adc_disable_scan_mode(ADC1);
|
|
|
|
|
adc_set_single_conversion_mode(ADC1);
|
|
|
|
|
adc_set_sample_time(ADC1, channel, ADC_SMPR_SMP_71DOT5CYC);
|
|
|
|
|
adc_disable_external_trigger_regular(ADC1);
|
|
|
|
|
adc_set_right_aligned(ADC1);
|
|
|
|
|
adc_set_regular_sequence(ADC1, 1, &channel);
|
|
|
|
|
adc_power_on(ADC1);
|
|
|
|
|
|
|
|
|
|
channel = ADC_CHANNEL1;
|
|
|
|
|
adc_disable_scan_mode(ADC2);
|
|
|
|
|
adc_set_single_conversion_mode(ADC2);
|
|
|
|
|
adc_set_sample_time(ADC2, channel, ADC_SMPR_SMP_71DOT5CYC);
|
|
|
|
|
adc_disable_external_trigger_regular(ADC2);
|
|
|
|
|
adc_set_right_aligned(ADC2);
|
|
|
|
|
adc_set_regular_sequence(ADC2, 1, &channel);
|
|
|
|
|
adc_power_on(ADC2);
|
|
|
|
|
|
|
|
|
|
/* Wait for ADC starting up. */
|
|
|
|
|
int i;
|
|
|
|
|
for (i = 0; i < 800000; i++) /* Wait a bit. */
|
|
|
|
|
__asm__("nop");
|
|
|
|
|
|
|
|
|
|
adc_reset_calibration(ADC1);
|
|
|
|
|
adc_calibration(ADC1);
|
|
|
|
|
adc_reset_calibration(ADC2);
|
|
|
|
|
adc_calibration(ADC2);
|
|
|
|
|
#endif
|
|
|
|
|
uint8_t channels[ADC_NUM_CHANNELS] = {
|
|
|
|
|
ADC_CHANNEL0, // VInSense
|
|
|
|
|
ADC_CHANNEL1, // VOutSense
|
|
|
|
@ -189,7 +158,7 @@ static void init_adc(void)
|
|
|
|
|
dma_enable_circular_mode(DMA1, DMA_CHANNEL1);
|
|
|
|
|
dma_set_read_from_peripheral(DMA1, DMA_CHANNEL1);
|
|
|
|
|
dma_set_peripheral_address(DMA1, DMA_CHANNEL1, (uint32_t) &ADC1_DR);
|
|
|
|
|
/* The array v[] is filled with the waveform data to be output */
|
|
|
|
|
/* The array adc_values[] is filled with the waveform data to be output */
|
|
|
|
|
dma_set_memory_address(DMA1, DMA_CHANNEL1, (uint32_t) adc_values);
|
|
|
|
|
dma_set_number_of_data(DMA1, DMA_CHANNEL1, ADC_NUM_CHANNELS);
|
|
|
|
|
//dma_enable_transfer_complete_interrupt(DMA1, DMA_CHANNEL1);
|
|
|
|
@ -418,38 +387,7 @@ void tim3_isr(void)
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#if 0
|
|
|
|
|
void tim4_isr(void)
|
|
|
|
|
{
|
|
|
|
|
uint32_t adcval, pwm_value;
|
|
|
|
|
|
|
|
|
|
// check for update interrupt
|
|
|
|
|
if(timer_interrupt_source(TIM4, TIM_SR_UIF)) {
|
|
|
|
|
// read ADC value
|
|
|
|
|
adcval = adc_read_regular(ADC2);
|
|
|
|
|
|
|
|
|
|
pwm_value = AUDIO_PWM_PERIOD * adcval / 4096;
|
|
|
|
|
timer_set_oc_value(TIM4, TIM_OC1, pwm_value);
|
|
|
|
|
timer_set_oc_value(TIM4, TIM_OC2, pwm_value);
|
|
|
|
|
|
|
|
|
|
dbg_audio_pwm_value = pwm_value;
|
|
|
|
|
|
|
|
|
|
// start conversion for next cycle
|
|
|
|
|
adc_start_conversion_direct(ADC2);
|
|
|
|
|
|
|
|
|
|
timer_clear_flag(TIM4, TIM_SR_UIF);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
void hard_fault_handler(void)
|
|
|
|
|
{
|
|
|
|
|
while (1);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
void usage_fault_handler(void)
|
|
|
|
|
{
|
|
|
|
|
while (1);
|
|
|
|
|
}
|
|
|
|
|
*/
|
|
|
|
|