deepsleep: use libopencm3 functions instead of register access

This commit is contained in:
Thomas Kolb 2021-06-12 01:10:41 +02:00
parent 98d0c08ec3
commit 189ea810d9
2 changed files with 12 additions and 15 deletions

View file

@ -6,6 +6,7 @@
#include "clock.h" #include "clock.h"
#include "deepsleep.h" #include "deepsleep.h"
#include "libopencm3/stm32/f0/rcc.h"
void init_rtc(void) void init_rtc(void)
{ {
@ -30,7 +31,7 @@ void init_rtc(void)
/* ?! Stdperiph examples don't turn this on until _afterwards_ which /* ?! Stdperiph examples don't turn this on until _afterwards_ which
* simply doesn't work. It must be on at least to be able to * simply doesn't work. It must be on at least to be able to
* configure it */ * configure it */
RCC_BDCR |= RCC_BDCR_RTCEN; rcc_enable_rtc_clock();
pwr_enable_backup_domain_write_protect(); pwr_enable_backup_domain_write_protect();
@ -43,13 +44,12 @@ void init_rtc(void)
static void unlock_rtc_access(void) static void unlock_rtc_access(void)
{ {
pwr_disable_backup_domain_write_protect(); pwr_disable_backup_domain_write_protect();
RTC_WPR = 0xCA; rtc_unlock();
RTC_WPR = 0x53;
} }
static void lock_rtc_access(void) static void lock_rtc_access(void)
{ {
RTC_WPR = 0xFF; rtc_lock();
pwr_enable_backup_domain_write_protect(); pwr_enable_backup_domain_write_protect();
} }
@ -61,12 +61,8 @@ void deepsleep(uint32_t duration_secs)
unlock_rtc_access(); unlock_rtc_access();
// enter initialization mode // enter initialization mode
RTC_ISR |= RTC_ISR_INIT; rtc_set_init_flag();
rtc_wait_for_init_ready();
// wait until initialization mode has been entered
while((RTC_ISR & RTC_ISR_INITF) != RTC_ISR_INITF) {
// do nothing
}
RTC_TR = 0; // 00:00:00 RTC_TR = 0; // 00:00:00
RTC_DR = // friday, 01.01.16 RTC_DR = // friday, 01.01.16
@ -116,20 +112,20 @@ void deepsleep(uint32_t duration_secs)
RTC_CR |= RTC_CR_ALRAE | RTC_CR_ALRAIE; RTC_CR |= RTC_CR_ALRAE | RTC_CR_ALRAIE;
// leave initialization mode // leave initialization mode
RTC_ISR &= ~RTC_ISR_INIT; rtc_clear_init_flag();
// lock registers again (using invalid key) // lock registers again (using invalid key)
lock_rtc_access(); lock_rtc_access();
// enter deep sleep mode // enter deep sleep mode
SCB_SCR |= SCB_SCR_SLEEPDEEP; SCB_SCR |= SCB_SCR_SLEEPDEEP;
PWR_CR |= PWR_CR_LPDS; // voltage regulator low-power mode pwr_voltage_regulator_low_power_in_stop();
pwr_set_stop_mode(); pwr_set_stop_mode();
__WFI(); __WFI();
SCB_SCR &= ~SCB_SCR_SLEEPDEEP; // no deepsleep except in this function SCB_SCR &= ~SCB_SCR_SLEEPDEEP; // no deepsleep except in this function
rcc_periph_clock_disable(RCC_PWR); // no longer needed //rcc_periph_clock_disable(RCC_PWR); // no longer needed
rcc_osc_off(RCC_LSI); //rcc_osc_off(RCC_LSI);
init_clock(); // ensure that all clocks are running again init_clock(); // ensure that all clocks are running again
} }

View file

@ -223,8 +223,9 @@ int main(void)
} else { } else {
// charge control already idle // charge control already idle
if((timebase_ms - charge_control_idle_since) > DEEPSLEEP_DELAY) { if((timebase_ms - charge_control_idle_since) > DEEPSLEEP_DELAY) {
rs485_enqueue("PWR:DEEPSLEEP"); rs485_enqueue("PWR:DEEPSLEEP:ENTRY\n");
deepsleep(DEEPSLEEP_DURATION); deepsleep(DEEPSLEEP_DURATION);
rs485_enqueue("PWR:DEEPSLEEP:EXIT\n");
charge_control_was_idle = false; charge_control_was_idle = false;
} }
} }