SolarLader/LNSC-2420
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First layout iteration completed

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All signals routed. DRC not yet run/fixed.
This commit is contained in:
Thomas Kolb 2021-05-06 21:25:37 +02:00
parent 2ae98ab46d
commit 0595ba2754
2 changed files with 2510 additions and 1482 deletions
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3964
LNSC-2420.kicad_pcb
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28
LNSC-2420.pro
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@ -1,4 +1,4 @@
update=Do 29 Apr 2021 22:21:03 CEST update=Mo 03 Mai 2021 22:54:51 CEST
version=1 version=1
last_client=kicad last_client=kicad
[general] [general]
@ -39,8 +39,12 @@ MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999 MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25 MinHoleToHole=0.25
TrackWidth1=0.25 TrackWidth1=0.25
TrackWidth2=0.25
TrackWidth3=0.5
ViaDiameter1=0.8 ViaDiameter1=0.8
ViaDrill1=0.4 ViaDrill1=0.4
ViaDiameter2=1.2
ViaDrill2=0.8
dPairWidth1=0.2 dPairWidth1=0.2
dPairGap1=0.25 dPairGap1=0.25
dPairViaGap1=0.25 dPairViaGap1=0.25
@ -246,3 +250,25 @@ uViaDrill=0.1
dPairWidth=0.2 dPairWidth=0.2
dPairGap=0.25 dPairGap=0.25
dPairViaGap=0.25 dPairViaGap=0.25
[pcbnew/Netclasses/1]
Name=HighPower
Clearance=0.3
TrackWidth=20
ViaDiameter=2
ViaDrill=1.2
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[pcbnew/Netclasses/2]
Name=Power
Clearance=0.3
TrackWidth=0.4
ViaDiameter=0.8
ViaDrill=0.4
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25