diff --git a/src/main.c b/src/main.c
index 383110e..d21133a 100644
--- a/src/main.c
+++ b/src/main.c
@@ -12,12 +12,16 @@
 #include "lcd.h"
 #include "debug.h"
 
+#define CONV_PWM_MAX 960
+
+#define TIM_CH_CONV      TIM_OC1
+#define TIM_CH_BOOTSTRAP TIM_OC2
+
 volatile int wait_frame = 1;
 
 #define ADC_NUM_CHANNELS 3
 volatile uint16_t adc_values[ADC_NUM_CHANNELS];
 
-
 static void init_gpio(void)
 {
 	// Set up UART TX on PB6 for debugging
@@ -42,7 +46,6 @@ static void init_gpio(void)
 static void init_clock(void)
 {
 	/* Set STM32 to 48 MHz. */
-	// DANGER WARNING: ABP Clock is sysclk/2!
 	// Relevant for Timers
 	//rcc_clock_setup_in_hse_8mhz_out_48mhz();
 	rcc_clock_setup_in_hsi_out_48mhz();
@@ -57,6 +60,9 @@ static void init_clock(void)
 	// enable TIM3 for scheduling
 	rcc_periph_clock_enable(RCC_TIM3);
 
+	// enable TIM1 for PWM generation
+	rcc_periph_clock_enable(RCC_TIM1);
+
 	// enable ADC1 clock
 	rcc_periph_clock_enable(RCC_ADC1);
 
@@ -66,67 +72,40 @@ static void init_clock(void)
 
 static void init_timer(void)
 {
-#if 0
-	// global interrupt config
-	nvic_enable_irq(NVIC_TIM1_UP_IRQ);
-	nvic_enable_irq(NVIC_TIM4_IRQ);
-
 	// *** TIM1 ***
-	// Generic scheduling
+	// Configure channels 1 and 2 for PWM (-> Pins PA8, PA9)
+	// Ch1 = Buck converter switch, Ch2 = bootstrap pulse
+	timer_reset(TIM1);
 
-	// - upcounter
-	// - clock: CK_INT
-	// - only overflow generates update interrupt
-	TIM1_CR1 |= TIM_CR1_URS;
-
-	// defaults for TIM_CR2
-
-	// enable update interrupt
-	TIM1_DIER |= TIM_DIER_UIE;
-
-	// prescaler
-	TIM1_PSC = 71; // count up by 1 every 1 us
-
-	// auto-reload (maximum value)
-	TIM1_ARR = 999; // overflow every 1 ms
-
-	// 48 kHz interrupt frequency
-	// TIM1_PSC = 24; // count up by 1 every 208.33 ns
-	// TIM1_ARR = 99; // multiply interval by 100 -> 20.833 us
-
-	// GO!
-	TIM1_CR1 |= TIM_CR1_CEN;
-
-	// *** TIM4 ***
-	// Configure channels 1 and 2 for PWM (-> Pins PB6, PB7)
-	// used for the boost converter switching
-	timer_reset(TIM4);
-
-	timer_set_mode(TIM4, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
+	timer_set_mode(TIM1, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
 
 	// set up PWM channels
-	timer_set_oc_mode(TIM4, TIM_OC1, TIM_OCM_PWM1);
-	timer_enable_oc_output(TIM4, TIM_OC1);
-	timer_enable_oc_preload(TIM4, TIM_OC1);
-	timer_set_oc_polarity_high(TIM4, TIM_OC1);
+	timer_set_oc_mode(TIM1, TIM_CH_CONV, TIM_OCM_PWM1);
+	timer_enable_oc_output(TIM1, TIM_CH_CONV);
+	timer_enable_oc_preload(TIM1, TIM_CH_CONV);
+	timer_set_oc_polarity_high(TIM1, TIM_CH_CONV);
 
-	timer_set_oc_mode(TIM4, TIM_OC2, TIM_OCM_PWM1);
-	timer_enable_oc_output(TIM4, TIM_OC2);
-	timer_enable_oc_preload(TIM4, TIM_OC2);
-	timer_set_oc_polarity_low(TIM4, TIM_OC2);
+	timer_set_oc_mode(TIM1, TIM_CH_BOOTSTRAP, TIM_OCM_PWM1);
+	timer_enable_oc_output(TIM1, TIM_CH_BOOTSTRAP);
+	timer_enable_oc_preload(TIM1, TIM_CH_BOOTSTRAP);
+	timer_set_oc_polarity_low(TIM1, TIM_CH_BOOTSTRAP);
+
+	timer_set_oc_value(TIM1, TIM_CH_CONV, 0); // no PWM by default
+	timer_set_oc_value(TIM1, TIM_CH_BOOTSTRAP, 0); // no PWM by default
+
+	// wanted: 50 kHz / 20 us period
+	// system clock: 48 MHz
+	// => 960 clock cycles / period = CONV_PWM_MAX
 
 	// prescaler
-	timer_set_prescaler(TIM4, AUDIO_PWM_PRESCALER - 1);
+	timer_set_prescaler(TIM1, 0); // Timer runs at system clock
 
 	// auto-reload value
-	timer_set_period(TIM4, AUDIO_PWM_PERIOD - 1); // -> PWM frequency = 120e6 / prescaler / period
+	timer_set_period(TIM1, CONV_PWM_MAX - 1);
 
 	// enable update interrupt (triggered on timer restart)
-	timer_enable_irq(TIM4, TIM_DIER_UIE);
+	//timer_enable_irq(TIM1, TIM_DIER_UIE);
 
-	// GO!
-	timer_enable_counter(TIM4);
-#endif
 	// *** TIM3 ***
 	// used for the 1-millisecond system tick
 	timer_reset(TIM3);