137 lines
3.0 KiB
C
137 lines
3.0 KiB
C
#include <libopencm3/stm32/rcc.h>
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#include <libopencm3/stm32/pwr.h>
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#include <libopencm3/stm32/rtc.h>
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#include <libopencmsis/core_cm3.h>
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#include <libopencm3/stm32/exti.h>
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#include "clock.h"
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#include "deepsleep.h"
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#include "libopencm3/stm32/f0/rcc.h"
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void init_rtc(void)
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{
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// RTC clock setup
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// see libopencm3-examples::examples/stm32/l1/stm32l-discovery/button-irq-printf-lowpower/main.c
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/* turn on power block to enable unlocking */
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rcc_periph_clock_enable(RCC_PWR);
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pwr_disable_backup_domain_write_protect();
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/* reset rtc */
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RCC_BDCR |= RCC_BDCR_BDRST;
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RCC_BDCR &= ~RCC_BDCR_BDRST;
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// use LSI for RTC
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rcc_osc_on(RCC_LSI);
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rcc_wait_for_osc_ready(RCC_LSI);
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/* Select the LSI as rtc clock */
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RCC_BDCR |= RCC_BDCR_RTCSEL_LSI;
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/* ?! Stdperiph examples don't turn this on until _afterwards_ which
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* simply doesn't work. It must be on at least to be able to
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* configure it */
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rcc_enable_rtc_clock();
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pwr_enable_backup_domain_write_protect();
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nvic_enable_irq(NVIC_RTC_IRQ);
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exti_set_trigger(EXTI17, EXTI_TRIGGER_RISING);
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exti_enable_request(EXTI17);
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}
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static void unlock_rtc_access(void)
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{
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pwr_disable_backup_domain_write_protect();
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rtc_unlock();
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}
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static void lock_rtc_access(void)
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{
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rtc_lock();
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pwr_enable_backup_domain_write_protect();
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}
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void deepsleep(uint32_t duration_secs)
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{
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uint32_t tmp = 0;
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// unlock RTC registers
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unlock_rtc_access();
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// enter initialization mode
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rtc_set_init_flag();
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rtc_wait_for_init_ready();
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RTC_TR = 0; // 00:00:00
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RTC_DR = // friday, 01.01.16
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(1 << RTC_DR_YT_SHIFT) |
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(6 << RTC_DR_YU_SHIFT) |
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(5 << RTC_DR_WDU_SHIFT) |
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(0 << RTC_DR_MT_SHIFT) |
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(1 << RTC_DR_MU_SHIFT) |
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(0 << RTC_DR_DT_SHIFT) |
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(1 << RTC_DR_DU_SHIFT);
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// disable Alarm A
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RTC_CR &= ~RTC_CR_ALRAE;
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// wait until register is writeable
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while((RTC_ISR & RTC_ISR_ALRAWF) != RTC_ISR_ALRAWF) {
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// do nothing
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}
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tmp |= (duration_secs % 10) << RTC_ALRMXR_SU_SHIFT;
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duration_secs /= 10;
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tmp |= (duration_secs % 6) << RTC_ALRMXR_ST_SHIFT;
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duration_secs /= 6;
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tmp |= (duration_secs % 10) << RTC_ALRMXR_MNU_SHIFT;
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duration_secs /= 10;
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tmp |= (duration_secs % 6) << RTC_ALRMXR_MNT_SHIFT;
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duration_secs /= 6;
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tmp |= (duration_secs % 10) << RTC_ALRMXR_HU_SHIFT;
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duration_secs /= 10;
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tmp |= (duration_secs % 2) << RTC_ALRMXR_HT_SHIFT;
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// FIXME: >1d is not supported
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tmp |= RTC_ALRMXR_MSK4; // ignore day/date
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// set alarm register
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RTC_ALRMAR = tmp;
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// clear Alarm A flag
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RTC_ISR &= ~RTC_ISR_ALRAF;
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// enable RTC alarm interrupt for wakeup
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RTC_CR |= RTC_CR_ALRAE | RTC_CR_ALRAIE;
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// leave initialization mode
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rtc_clear_init_flag();
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// lock registers again (using invalid key)
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lock_rtc_access();
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// enter deep sleep mode
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pwr_set_stop_mode();
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pwr_voltage_regulator_low_power_in_stop();
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SCB_SCR |= SCB_SCR_SLEEPDEEP;
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__WFI();
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SCB_SCR &= ~SCB_SCR_SLEEPDEEP; // no deepsleep except in this function
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//rcc_periph_clock_disable(RCC_PWR); // no longer needed
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//rcc_osc_off(RCC_LSI);
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init_clock(); // ensure that all clocks are running again
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}
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void rtc_isr(void)
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{
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exti_reset_request(EXTI17);
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}
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